Specification	SN74ACT373PW

Circuit [custom]	8
Circuit [custom]	8
Current - Output High, Low	24 mA
Delay Time - Propagation	8.5 ns
Independent Circuits	1
Logic Type	D-Type Transparent Latch
Mounting Type	Surface Mount
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output Type	Tri-State
Package / Case	20-TSSOP
Package / Case [x]	0.173 in
Package / Case [y]	4.4 mm
Supplier Device Package	20-TSSOP
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	4.5 V

SN74ACT373-EP Series

Enhanced Product Octal D-Type Transparent Latches With 3-State Outputs

Part	Operating Temperature [Max]	Operating Temperature [Min]	Independent Circuits	Supplier Device Package	Output Type	Package / Case [y]	Package / Case	Package / Case [x]	Mounting Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Logic Type	Circuit [custom]	Circuit [custom]	Delay Time - Propagation	Current - Output High, Low	Package / Case [y]	Package / Case	Package / Case
Texas Instruments SN74ACT373PW	85 °C	-40 °C	1	20-TSSOP	Tri-State	4.4 mm	20-TSSOP	0.173 in	Surface Mount	4.5 V	5.5 V	D-Type Transparent Latch	8	8	8.5 ns	24 mA
Texas Instruments CD74ACT373M96	125 °C	-55 °C	1	20-SOIC	Tri-State	0.295 in	20-SOIC		Surface Mount	4.5 V	5.5 V	D-Type Transparent Latch	8	8	3 ns	24 mA	7.5 mm
Texas Instruments SN74ACT373NSR	85 °C	-40 °C	1	20-SO	Tri-State		20-SOIC		Surface Mount	4.5 V	5.5 V	D-Type Transparent Latch	8	8	8.5 ns	24 mA		0.209 "	5.3 mm
Texas Instruments SN74ACT373DW	85 °C	-40 °C	1	20-SOIC	Tri-State	0.295 in	20-SOIC		Surface Mount	4.5 V	5.5 V	D-Type Transparent Latch	8	8	8.5 ns	24 mA	7.5 mm
Texas Instruments CD74ACT373M96E4	125 °C	-55 °C	1	20-SOIC	Tri-State	0.295 in	20-SOIC		Surface Mount	4.5 V	5.5 V	D-Type Transparent Latch	8	8	3 ns	24 mA	7.5 mm
Texas Instruments CD74ACT373E	125 °C	-55 °C	1	20-PDIP	Tri-State		20-DIP		Through Hole	4.5 V	5.5 V	D-Type Transparent Latch	8	8	3 ns	24 mA		0.3 in	7.62 mm
Texas Instruments CD74ACT373M	125 °C	-55 °C	1	20-SOIC	Tri-State	0.295 in	20-SOIC		Surface Mount	4.5 V	5.5 V	D-Type Transparent Latch	8	8	3 ns	24 mA	7.5 mm
Texas Instruments CD74ACT373EG4	125 °C	-55 °C	1	20-PDIP	Tri-State		20-DIP		Through Hole	4.5 V	5.5 V	D-Type Transparent Latch	8	8	3 ns	24 mA		0.3 in	7.62 mm
Texas Instruments SN74ACT373MDWREP	125 °C	-55 °C	1	20-SOIC	Tri-State	0.295 in	20-SOIC		Surface Mount	4.5 V	5.5 V	D-Type Transparent Latch	8	8	8.5 ns	24 mA	7.5 mm
Texas Instruments SN74ACT373PWR	85 °C	-40 °C	1	20-TSSOP	Tri-State	4.4 mm	20-TSSOP	0.173 in	Surface Mount	4.5 V	5.5 V	D-Type Transparent Latch	8	8	8.5 ns	24 mA

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tube	1	$ 1.16
		10	$ 1.04
		70	$ 0.99
		140	$ 0.81
		280	$ 0.76
		560	$ 0.67
Texas Instruments	TUBE	1	$ 0.86
		100	$ 0.66
		250	$ 0.49
		1000	$ 0.35

Description

General part information

SN74ACT373-EP Series

This 8-bit latch features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight latches are D-type transparent latches. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines in bus-organized systems without need for interface or pullup components.

Documents

Technical documentation and resources

SNx4ACT373 Octal D-Type Transparent Latches with 3-State Outputs datasheet (Rev. F)

Data sheet

Implications of Slow or Floating CMOS Inputs (Rev. E)

Application note

Selecting the Right Level Translation Solution (Rev. A)

Application note

CMOS Power Consumption and CPD Calculation (Rev. B)

Application note

SN74ACT373PW

Deep-Dive with AI

SN74ACT373PW

Deep-Dive with AI

Technical Specifications

SN74ACT373-EP Series

Pricing

Description

SN74ACT373-EP Series

Documents

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Logic Guide (Rev. AB)

Power-Up Behavior of Clocked Devices (Rev. B)

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc

LOGIC Pocket Data Book (Rev. B)

Designing With Logic (Rev. C)

TI IBIS File Creation, Validation, and Distribution Processes

SNx4ACT373 Octal D-Type Transparent Latches with 3-State Outputs datasheet (Rev. F)

Implications of Slow or Floating CMOS Inputs (Rev. E)

Selecting the Right Level Translation Solution (Rev. A)

CMOS Power Consumption and CPD Calculation (Rev. B)

SN74ACT373-EP Series