
SN74HC377N
ActiveFLIP FLOP D-TYPE BUS INTERFACE POS-EDGE 1-ELEMENT 20-PIN PDIP TUBE
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SN74HC377N
ActiveFLIP FLOP D-TYPE BUS INTERFACE POS-EDGE 1-ELEMENT 20-PIN PDIP TUBE
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74HC377N |
|---|---|
| Clock Frequency | 64 MHz |
| Current - Output High, Low [custom] | 5.2 mA |
| Current - Output High, Low [custom] | 5.2 mA |
| Current - Quiescent (Iq) | 8 ÁA |
| Function | Standard |
| Input Capacitance | 3 pF |
| Max Propagation Delay @ V, Max CL | 27 ns |
| Mounting Type | Through Hole |
| Number of Bits per Element | 8 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Non-Inverted |
| Package / Case | 20-DIP |
| Package / Case | 7.62 mm |
| Package / Case | 0.3 in |
| Supplier Device Package | 20-PDIP |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 6 V |
| Voltage - Supply [Min] | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Arrow | N/A | 1 | $ 1.05 | |
| 10 | $ 0.66 | |||
| 50 | $ 0.61 | |||
| 100 | $ 0.57 | |||
| 200 | $ 0.56 | |||
| Digikey | Tube | 1 | $ 1.45 | |
| 20 | $ 1.30 | |||
| 40 | $ 1.23 | |||
| 100 | $ 1.01 | |||
| 260 | $ 0.95 | |||
| 500 | $ 0.84 | |||
| 1000 | $ 0.66 | |||
| 2500 | $ 0.62 | |||
| 5000 | $ 0.59 | |||
| Texas Instruments | TUBE | 1 | $ 1.08 | |
| 100 | $ 0.83 | |||
| 250 | $ 0.61 | |||
| 1000 | $ 0.44 | |||
Description
General part information
SN74HC377A Series
The ’HC377 and ’HCT377 are octal D-type flip-flops with a buffered clock (CP) common to all eight flip-flops. All the flip-flops are loaded simultaneously on the positive edge of the clock (CP) when the Data Enable (E\) is Low.
The ’HC377 and ’HCT377 are octal D-type flip-flops with a buffered clock (CP) common to all eight flip-flops. All the flip-flops are loaded simultaneously on the positive edge of the clock (CP) when the Data Enable (E\) is Low.
Documents
Technical documentation and resources