
SN74HC377ANSR
ActiveOCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE
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SN74HC377ANSR
ActiveOCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE
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Technical Specifications
Parameters and characteristics for this part
| Specification | SN74HC377ANSR |
|---|---|
| Clock Frequency | 71 MHz |
| Current - Output High, Low [custom] | 5.2 mA |
| Current - Output High, Low [custom] | 5.2 mA |
| Current - Quiescent (Iq) | 8 ÁA |
| Function | Standard |
| Input Capacitance | 3 pF |
| Max Propagation Delay @ V, Max CL | 24 ns |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 8 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Non-Inverted |
| Package / Case | 20-SOIC |
| Package / Case | 0.209 " |
| Package / Case | 5.3 mm |
| Supplier Device Package | 20-SO |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 6 V |
| Voltage - Supply [Min] | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 0.84 | |
| 10 | $ 0.74 | |||
| 25 | $ 0.70 | |||
| 100 | $ 0.57 | |||
| 250 | $ 0.53 | |||
| 500 | $ 0.45 | |||
| 1000 | $ 0.36 | |||
| Digi-Reel® | 1 | $ 0.84 | ||
| 10 | $ 0.74 | |||
| 25 | $ 0.70 | |||
| 100 | $ 0.57 | |||
| 250 | $ 0.53 | |||
| 500 | $ 0.45 | |||
| 1000 | $ 0.36 | |||
| Tape & Reel (TR) | 2000 | $ 0.28 | ||
| Texas Instruments | LARGE T&R | 1 | $ 0.63 | |
| 100 | $ 0.49 | |||
| 250 | $ 0.36 | |||
| 1000 | $ 0.26 | |||
Description
General part information
SN74HC377A Series
The ’HC377 and ’HCT377 are octal D-type flip-flops with a buffered clock (CP) common to all eight flip-flops. All the flip-flops are loaded simultaneously on the positive edge of the clock (CP) when the Data Enable (E\) is Low.
The ’HC377 and ’HCT377 are octal D-type flip-flops with a buffered clock (CP) common to all eight flip-flops. All the flip-flops are loaded simultaneously on the positive edge of the clock (CP) when the Data Enable (E\) is Low.
Documents
Technical documentation and resources
No documents available