
CD74HC377PWR
ActiveHIGH SPEED CMOS LOGIC OCTAL D-TYPE FLIP-FLOPS WITH DATA ENABLE
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CD74HC377PWR
ActiveHIGH SPEED CMOS LOGIC OCTAL D-TYPE FLIP-FLOPS WITH DATA ENABLE
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Technical Specifications
Parameters and characteristics for this part
| Specification | CD74HC377PWR |
|---|---|
| Clock Frequency | 60 MHz |
| Current - Output High, Low [custom] | 5.2 mA |
| Current - Output High, Low [custom] | 5.2 mA |
| Current - Quiescent (Iq) | 8 ÁA |
| Function | Standard |
| Input Capacitance | 10 pF |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 8 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Output Type | Non-Inverted |
| Package / Case | 20-TSSOP |
| Package / Case [x] | 0.173 in |
| Package / Case [y] | 4.4 mm |
| Supplier Device Package | 20-TSSOP |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 6 V |
| Voltage - Supply [Min] | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 0.71 | |
| 10 | $ 0.62 | |||
| 25 | $ 0.58 | |||
| 100 | $ 0.48 | |||
| 250 | $ 0.44 | |||
| 500 | $ 0.38 | |||
| 1000 | $ 0.30 | |||
| Digi-Reel® | 1 | $ 0.71 | ||
| 10 | $ 0.62 | |||
| 25 | $ 0.58 | |||
| 100 | $ 0.48 | |||
| 250 | $ 0.44 | |||
| 500 | $ 0.38 | |||
| 1000 | $ 0.30 | |||
| Tape & Reel (TR) | 2000 | $ 0.27 | ||
| 6000 | $ 0.25 | |||
| 10000 | $ 0.25 | |||
| Texas Instruments | LARGE T&R | 1 | $ 0.45 | |
| 100 | $ 0.34 | |||
| 250 | $ 0.25 | |||
| 1000 | $ 0.18 | |||
Description
General part information
SN74HC377A Series
The ’HC377 and ’HCT377 are octal D-type flip-flops with a buffered clock (CP) common to all eight flip-flops. All the flip-flops are loaded simultaneously on the positive edge of the clock (CP) when the Data Enable (E\) is Low.
The ’HC377 and ’HCT377 are octal D-type flip-flops with a buffered clock (CP) common to all eight flip-flops. All the flip-flops are loaded simultaneously on the positive edge of the clock (CP) when the Data Enable (E\) is Low.
Documents
Technical documentation and resources