LAN91C111I-NS
ActiveETHERNET CONTROLLER, MAC & PHY ETHERNET CONTROLLER, IEEE 802.3, IEEE 802.3U, 2.97 V, 3.63 V, QFP
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LAN91C111I-NS
ActiveETHERNET CONTROLLER, MAC & PHY ETHERNET CONTROLLER, IEEE 802.3, IEEE 802.3U, 2.97 V, 3.63 V, QFP
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Technical Specifications
Parameters and characteristics for this part
| Specification | LAN91C111I-NS |
|---|---|
| Function | Controller |
| Interface | Parallel |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 128-BFQFP |
| Protocol | Ethernet |
| Standards | 10/100 Base-T/TX PHY |
| Supplier Device Package | 128-QFP (14x20) |
| Voltage - Supply | 3.3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tray | 1 | $ 37.61 | |
| 25 | $ 31.34 | |||
| 100 | $ 30.27 | |||
| Microchip Direct | TRAY | 1 | $ 37.61 | |
| 25 | $ 31.34 | |||
| 100 | $ 28.50 | |||
| 1000 | $ 27.52 | |||
| 5000 | $ 27.22 | |||
| Newark | Each | 25 | $ 31.92 | |
| 100 | $ 29.36 | |||
Description
General part information
LAN91C111 Series
The Microchip LAN91C111 is designed to facilitate the implementation of a third generation of Fast Ethernet connectivity solutions for embedded applications. For this third generation of products, flexibility and integration dominate the design requirements. The LAN91C111 is a mixed signal Analog/Digital device that implements the MAC and PHY portion of the CSMA/CD protocol at 10 and 100 Mbps. The design will also minimize data throughput constraints utilizing a 32-bit, 16-bit or 8-bit bus Host interface in embedded applications.
The total internal memory FIFO buffer size is 8 Kbytes, which is the total chip storage for transmit and receive operations.
The Microchip LAN91C111 is software compatible with the LAN9000 family of products.
Documents
Technical documentation and resources
