DS80EP100SD/NOPB
Active5 TO 12.5-GBPS, POWER-SAVER EQUALIZER FOR BACKPLANES AND CABLES
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DS80EP100SD/NOPB
Active5 TO 12.5-GBPS, POWER-SAVER EQUALIZER FOR BACKPLANES AND CABLES
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | DS80EP100SD/NOPB |
|---|---|
| Applications | Displays |
| Interface | Coax Cable, Female Connector |
| Mounting Type | Surface Mount |
| Supplier Device Package | 6-WSON (2.2x2.5) |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 2.75 | |
| Digi-Reel® | 1 | $ 2.75 | ||
| Tape & Reel (TR) | 1000 | $ 1.35 | ||
| 2000 | $ 1.26 | |||
| 5000 | $ 1.21 | |||
| Texas Instruments | SMALL T&R | 1 | $ 1.87 | |
| 100 | $ 1.64 | |||
| 250 | $ 1.15 | |||
| 1000 | $ 0.92 | |||
Description
General part information
DS80EP100 Series
TI’s Power-saver equalizer compensates for transmission medium losses and minimizes medium-induced deterministic jitter. Performance is guaranteed over the full range of 5 to 12.5 Gbps. The DS80EP100 requires no power to operate. The equalizer operates anywhere in the data path to minimize media-induced deterministic jitter in both FR4 traces and cable applications. Symmetric I/O structures support full duplex or half duplex applications. Linear compensation is provided independent of line coding or protocol. The device is ideal for both bi-level and multi-level signaling.
The equalizer is available in a 6 pin leadless WSON package with a space saving 2.2 mm X 2.5 mm footprint. This tiny package provides maximum flexibility in placement and routing of the Power-saver equalizer.
TI’s Power-saver equalizer compensates for transmission medium losses and minimizes medium-induced deterministic jitter. Performance is guaranteed over the full range of 5 to 12.5 Gbps. The DS80EP100 requires no power to operate. The equalizer operates anywhere in the data path to minimize media-induced deterministic jitter in both FR4 traces and cable applications. Symmetric I/O structures support full duplex or half duplex applications. Linear compensation is provided independent of line coding or protocol. The device is ideal for both bi-level and multi-level signaling.
Documents
Technical documentation and resources
