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Texas Instruments-ADS42LB69IRGCR Analog to Digital Converters - ADCs 2-Channel Dual ADC Pipelined 250Msps 16-bit LVDS 64-Pin VQFN EP T/R
Integrated Circuits (ICs)

ADS42JB49IRGCR

Active
Texas Instruments

2-CHANNEL DUAL ADC PIPELINED 250MSPS 14-BIT JESD204B 64-PIN VQFN EP T/R

Texas Instruments-ADS42LB69IRGCR Analog to Digital Converters - ADCs 2-Channel Dual ADC Pipelined 250Msps 16-bit LVDS 64-Pin VQFN EP T/R
Integrated Circuits (ICs)

ADS42JB49IRGCR

Active
Texas Instruments

2-CHANNEL DUAL ADC PIPELINED 250MSPS 14-BIT JESD204B 64-PIN VQFN EP T/R

Technical Specifications

Parameters and characteristics for this part

SpecificationADS42JB49IRGCR
Mounting TypeSurface Mount
Package / Case64-VFQFN Exposed Pad
Supplier Device Package64-VQFN (9x9)

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTape & Reel (TR) 2000$ 151.25
Texas InstrumentsLARGE T&R 1$ 140.36
100$ 127.05
250$ 123.42
1000$ 121.00

Description

General part information

ADS42JB49 Series

The ADS42JB69 and ADS42JB49 are high-linearity, dual-channel, 16- and 14-bit, 250-MSPS, analog-to-digital converters (ADCs). These devices support the JESD204B serial interface with data rates up to3.125 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy making it easy to drive analog inputs up to very high input frequencies. A sampling clock divider allows more flexibility for system clock architecture design. The devices employ internal dither algorithms to provide excellent spurious-free dynamic range (SFDR) over a large input frequency range.

The ADS42JB69 and ADS42JB49 are high-linearity, dual-channel, 16- and 14-bit, 250-MSPS, analog-to-digital converters (ADCs). These devices support the JESD204B serial interface with data rates up to3.125 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy making it easy to drive analog inputs up to very high input frequencies. A sampling clock divider allows more flexibility for system clock architecture design. The devices employ internal dither algorithms to provide excellent spurious-free dynamic range (SFDR) over a large input frequency range.