CD4502BPW
ActiveBUFFER/DRIVER 6-CH INVERTING 3-ST CMOS 16-PIN TSSOP TUBE
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CD4502BPW
ActiveBUFFER/DRIVER 6-CH INVERTING 3-ST CMOS 16-PIN TSSOP TUBE
Technical Specifications
Parameters and characteristics for this part
| Specification | CD4502BPW |
|---|---|
| Current - Output High, Low [custom] | 3.4 mA |
| Current - Output High, Low [custom] | 20.4 mA |
| Logic Type | Inverting, Buffer |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 6 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Output Type | Push-Pull |
| Package / Case | 16-TSSOP |
| Package / Case [x] | 0.173 in |
| Package / Case [y] | 4.4 mm |
| Supplier Device Package | 16-TSSOP |
| Voltage - Supply [Max] | 18 V |
| Voltage - Supply [Min] | 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tube | 1 | $ 0.38 | |
| 10 | $ 0.32 | |||
| 90 | $ 0.24 | |||
| 270 | $ 0.22 | |||
| 540 | $ 0.19 | |||
| 1080 | $ 0.15 | |||
| Texas Instruments | TUBE | 1 | $ 0.80 | |
| 100 | $ 0.54 | |||
| 250 | $ 0.42 | |||
| 1000 | $ 0.28 | |||
Description
General part information
CD4502B Series
CD4502B consists of six inverter/buffers with 3-state outputs. A logic "1" on the OUTPUT DISABLE input produces a high-impedance state in all six outputs. This feature permits common busing of the outputs, thus simplifying system design. A Logic "1" on the INHIBIT input switches all six outputs to logic "0" if the OUTPUT DISABLE input is a logic "0". This device is capable of driving two standard TTL loads, which is equivalent to six times the JEDEC "B"-series IOLstandard.
The CD4502B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
CD4502B consists of six inverter/buffers with 3-state outputs. A logic "1" on the OUTPUT DISABLE input produces a high-impedance state in all six outputs. This feature permits common busing of the outputs, thus simplifying system design. A Logic "1" on the INHIBIT input switches all six outputs to logic "0" if the OUTPUT DISABLE input is a logic "0". This device is capable of driving two standard TTL loads, which is equivalent to six times the JEDEC "B"-series IOLstandard.
Documents
Technical documentation and resources
