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16 WQFN
Integrated Circuits (ICs)

SN74HCS595QBQBRQ1

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Texas Instruments

AUTOMOTIVE 8-BIT SHIFT REGISTER WITH SCHMITT-TRIGGER INPUTS AND 3-STATE OUTPUT REGISTERS

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16 WQFN
Integrated Circuits (ICs)

SN74HCS595QBQBRQ1

Active
Texas Instruments

AUTOMOTIVE 8-BIT SHIFT REGISTER WITH SCHMITT-TRIGGER INPUTS AND 3-STATE OUTPUT REGISTERS

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74HCS595QBQBRQ1
FunctionSerial to Parallel
GradeAutomotive
Logic TypeShift Register
Mounting TypeSurface Mount
Number of Bits per Element8
Number of Elements1
Operating Temperature [Max]125 °C
Operating Temperature [Min]-40 °C
Output TypeTri-State
Package / Case16-WFQFN Exposed Pad
QualificationAEC-Q100
Supplier Device Package16-WQFN (2.5x3.5)
Voltage - Supply [Max]6 V
Voltage - Supply [Min]2 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 0.44
10$ 0.39
25$ 0.37
100$ 0.30
250$ 0.28
500$ 0.24
1000$ 0.21
Digi-Reel® 1$ 0.44
10$ 0.39
25$ 0.37
100$ 0.30
250$ 0.28
500$ 0.24
1000$ 0.21
Tape & Reel (TR) 3000$ 0.21
Texas InstrumentsLARGE T&R 1$ 0.48
100$ 0.32
250$ 0.25
1000$ 0.17

Description

General part information

SN74HCS595-Q1 Series

The SN74HCS595-Q1 device contains an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. All inputs include Schmitt-trigger architecture, eliminating any erroneous data outputs due to slow-edged or noisy input signals. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output (QH’) for cascading. When the output-enable (OE) input is high, the storage register outputs are in a high-impedance state. Internal register data and serial output (QH’) are not impacted by the operation of theOEinput.

The SN74HCS595-Q1 device contains an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. All inputs include Schmitt-trigger architecture, eliminating any erroneous data outputs due to slow-edged or noisy input signals. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output (QH’) for cascading. When the output-enable (OE) input is high, the storage register outputs are in a high-impedance state. Internal register data and serial output (QH’) are not impacted by the operation of theOEinput.