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64-LFCSP-VQ
Integrated Circuits (ICs)

AD9648TCPZ-125-EP

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Analog Devices

14-BIT, 125 MSPS/105 MSPS, 1.8 V DUAL ANALOG-TO-DIGITAL CONVERTER

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64-LFCSP-VQ
Integrated Circuits (ICs)

AD9648TCPZ-125-EP

Active
Analog Devices

14-BIT, 125 MSPS/105 MSPS, 1.8 V DUAL ANALOG-TO-DIGITAL CONVERTER

Technical Specifications

Parameters and characteristics for this part

SpecificationAD9648TCPZ-125-EP
ArchitecturePipelined
ConfigurationS/H-ADC
Data InterfaceLVDS - Parallel, Parallel
FeaturesSimultaneous Sampling
Input TypeDifferential
Mounting TypeSurface Mount
Number of A/D Converters2
Number of Bits14
Number of Inputs2
Operating Temperature [Max]125 °C
Operating Temperature [Min]-55 °C
Package / Case64-WFQFN Exposed Pad, CSP
Ratio - S/H:ADC1:1
Reference TypeExternal, Internal
Sampling Rate (Per Second)125 M
Supplier Device Package64-LFCSP (9x9)
Voltage - Supply, Analog [Max]1.9 V
Voltage - Supply, Analog [Min]1.7 V
Voltage - Supply, Digital [Max]1.9 V
Voltage - Supply, Digital [Min]1.7 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTray 1$ 159.75
10$ 131.93
25$ 128.49

Description

General part information

AD9648 Series

The AD9648 is a monolithic, dual-channel, 1.8 V supply, 14-bit, 105 MSPS/125 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference. The product uses multistage differential pipeline architecture with output error correction logic to provide 14-bit accuracy at 125 MSPS data rates and to guarantee no missing codes over the full operating temperature range.The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.The digital output data is presented in offset binary, Gray code, or twos complement format. A data output clock (DCO) is provided for each ADC channel to ensure proper latch timing with receiving logic. Output logic levels of 1.8 V CMOS or LVDS are supported. Output data can also be multiplexed onto a single output bus.The AD9648 is available in a 64-lead RoHS compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C).ApplicationsCommunicationsDiversity radio systemsMultimode digital receiversGSM, EDGE, W-CDMA, LTE,CDMA2000, WiMAX, TD-SCDMAI/Q demodulation systemsSmart antenna systemsBroadband data applicationsBattery-powered instrumentsHand held scope metersPortable medical imagingUltrasoundRadar/LIDARProduct HighlightsThe AD9648 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V CMOS or LVDS logic families.The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use.A standard serial port interface supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO/data timing and offset adjustments.The AD9648 is packaged in a 64-lead RoHS compliant LFCSP that is pin compatible with theAD9650/AD9269/AD926816-bit ADC’s, theAD925814-bit ADC, theAD9628/AD923112-bit ADC’s, and theAD9608/AD920410-bit ADC’s, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS.