
SN74LVC823APWT
ActiveFLIP FLOP D-TYPE BUS INTERFACE POS-EDGE 3-ST 1-ELEMENT 24-PIN TSSOP T/R
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SN74LVC823APWT
ActiveFLIP FLOP D-TYPE BUS INTERFACE POS-EDGE 3-ST 1-ELEMENT 24-PIN TSSOP T/R
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74LVC823APWT |
|---|---|
| Clock Frequency | 150 MHz |
| Current - Output High, Low | 24 mA |
| Current - Quiescent (Iq) | 10 µA |
| Input Capacitance | 5 pF |
| Max Propagation Delay @ V, Max CL | 8 ns |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 9 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Tri-State, Non-Inverted |
| Package / Case | 24-TSSOP |
| Package / Case | 0.173 in, 4.4 mm |
| Supplier Device Package | 24-TSSOP |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 1.65 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 1.22 | |
| 10 | $ 1.09 | |||
| 25 | $ 1.04 | |||
| 100 | $ 0.85 | |||
| Digi-Reel® | 1 | $ 1.22 | ||
| 10 | $ 1.09 | |||
| 25 | $ 1.04 | |||
| 100 | $ 0.85 | |||
| Tape & Reel (TR) | 250 | $ 0.79 | ||
| 500 | $ 0.70 | |||
| 1250 | $ 0.55 | |||
| 2500 | $ 0.52 | |||
| 6250 | $ 0.49 | |||
| 12500 | $ 0.47 | |||
| Texas Instruments | SMALL T&R | 1 | $ 0.90 | |
| 100 | $ 0.69 | |||
| 250 | $ 0.51 | |||
| 1000 | $ 0.37 | |||
Description
General part information
SN74LVC823A Series
This 9-bit bus-interface flip-flop is designed for 1.65-V to 3.6-V VCCoperation.
The SN74LVC823A is designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.
With the clock-enable (CLKEN)\ input low, the nine D-type edge-triggered flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN\ high disables the clock buffer, latching the outputs. This device has noninverting data (D) inputs. Taking the clear (CLR)\ input low causes the nine Q outputs to go low, independently of the clock.
Documents
Technical documentation and resources