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20-SOIC,DW
Integrated Circuits (ICs)

SN74LVC823ADW

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Texas Instruments

FLIP FLOP D-TYPE BUS INTERFACE POS-EDGE 3-ST 1-ELEMENT 24-PIN SOIC TUBE

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20-SOIC,DW
Integrated Circuits (ICs)

SN74LVC823ADW

Active
Texas Instruments

FLIP FLOP D-TYPE BUS INTERFACE POS-EDGE 3-ST 1-ELEMENT 24-PIN SOIC TUBE

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74LVC823ADW
Clock Frequency150 MHz
Current - Output High, Low24 mA
Current - Quiescent (Iq)10 µA
Input Capacitance5 pF
Max Propagation Delay @ V, Max CL8 ns
Mounting TypeSurface Mount
Number of Bits per Element9
Number of Elements1
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Output TypeTri-State, Non-Inverted
Package / Case24-SOIC
Package / Case [custom]7.5 mm
Package / Case [custom]0.295 in
Supplier Device Package24-SOIC
Trigger TypePositive Edge
TypeD-Type
Voltage - Supply [Max]3.6 V
Voltage - Supply [Min]1.65 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1$ 0.89
10$ 0.80
25$ 0.76
100$ 0.62
250$ 0.58
500$ 0.51
1000$ 0.48
Texas InstrumentsTUBE 1$ 0.94
100$ 0.72
250$ 0.53
1000$ 0.38

Description

General part information

SN74LVC823A Series

This 9-bit bus-interface flip-flop is designed for 1.65-V to 3.6-V VCCoperation.

The SN74LVC823A is designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.

With the clock-enable (CLKEN)\ input low, the nine D-type edge-triggered flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN\ high disables the clock buffer, latching the outputs. This device has noninverting data (D) inputs. Taking the clear (CLR)\ input low causes the nine Q outputs to go low, independently of the clock.

Documents

Technical documentation and resources

Power-Up Behavior of Clocked Devices (Rev. B)

Application note

Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices

Application note

Live Insertion

Application note

TI IBIS File Creation, Validation, and Distribution Processes

Application note

Standard Linear & Logic for PCs, Servers & Motherboards

More literature

SN74LVC823A datasheet (Rev. I)

Data sheet

Implications of Slow or Floating CMOS Inputs (Rev. E)

Application note

Signal Switch Data Book (Rev. A)

User guide

STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS

More literature

16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)

Application note

LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)

User guide

Understanding Advanced Bus-Interface Products Design Guide

Application note

LOGIC Pocket Data Book (Rev. B)

User guide

Design Summary for WCSP Little Logic (Rev. B)

Product overview

LVC Characterization Information

Application note

Little Logic Guide 2018 (Rev. G)

Selection guide

Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices

Application note

Low-Voltage Logic (LVC) Designer's Guide

Design guide

Selecting the Right Level Translation Solution (Rev. A)

Application note

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Application note

Logic Guide (Rev. AB)

Selection guide

Input and Output Characteristics of Digital Integrated Circuits

Application note

CMOS Power Consumption and CPD Calculation (Rev. B)

Application note

Use of the CMOS Unbuffered Inverter in Oscillator Circuits

Application note

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Application note

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Application note

Texas Instruments Little Logic Application Report

Application note

How to Select Little Logic (Rev. A)

Application note