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ADC09DJ800AAVTQ1
Integrated Circuits (ICs)

ADC12DJ4000RFZEG

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Texas Instruments

2-CHANNEL DUAL ADC FOLDING/INTERPOLATING 8GSPS 12-BIT JESD204B/JESD204C 144-PIN FCBGA TRAY

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ADC09DJ800AAVTQ1
Integrated Circuits (ICs)

ADC12DJ4000RFZEG

Active
Texas Instruments

2-CHANNEL DUAL ADC FOLDING/INTERPOLATING 8GSPS 12-BIT JESD204B/JESD204C 144-PIN FCBGA TRAY

Technical Specifications

Parameters and characteristics for this part

SpecificationADC12DJ4000RFZEG
ArchitectureSAR
ConfigurationADC
Data InterfaceJESD204B/C
Input TypeDifferential
Mounting TypeSurface Mount
Number of A/D Converters2
Number of Bits12 bits
Number of Inputs8
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Ratio - S/H:ADC2:2
Reference TypeExternal
Supplier Device Package144-FCBGA
Voltage - Supply, Analog [Max]2 V, 1.15 V
Voltage - Supply, Analog [Min]1.8 V, 1.05 V
Voltage - Supply, Digital [Max]1.15 V
Voltage - Supply, Digital [Min]1.05 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTray 1$ 2226.77
Texas InstrumentsJEDEC TRAY (5+1) 1$ 2083.20
100$ 1909.60
250$ 1805.44
1000$ 1736.00

Description

General part information

ADC12DJ4000RF Series

The ADC12DJ4000RF device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. ADC12DJ4000RF can be configured as a dual-channel, 4 GSPS ADC or single-channel, 8 GSPS ADC. Support of a useable input frequency range of up to 10GHz enables direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DJ4000RF uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers.

Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multi-channel applications. Optional digital down converters (DDCs) are available to provide digital conversion to baseband and to reduce the interface rate. A programmable FIR filter allows on-chip equalization.