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ADC12DJ4000RF

ADC12DJ4000RF Series

RF-sampling 12-bit ADC with 4-GSPS dual channel or 8-GSPS single channel

Manufacturer: Texas Instruments

Catalog

RF-sampling 12-bit ADC with 4-GSPS dual channel or 8-GSPS single channel

Key Features

ADC core:12-bit resolutionUp to 8GSPS in single-channel modeUp to 4GSPS in dual-channel modePerformance specifications:Noise floor (–20dBFS, VFS = 1VPP-DIFF):Dual-channel mode: –152.3dBFS/HzSingle-channel mode: –155dBFS/HzENOB (dual channel, FIN = 2.4GHz): 8.8 BitsBuffered analog inputs with VCMI of 0 V:Analog input bandwidth (–3dB): 8GHzUsable input frequency range: > 10GHzFull-scale input voltage (VFS, default): 0.8VPPNoiseless aperture delay (tAD) adjustment:Precise sampling control: 19fs StepSimplifies synchronization and interleavingTemperature and voltage invariant delaysEasy-to-use synchronization features:Automatic SYSREF timing calibrationTimestamp for sample markingJESD204C serial data interface:Maximum lane rate: 17.16GbpsSupport for 64b/66b and 8b/10b encoding8b/10b modes are JESD204B compatibleOptional digital down-converters (DDC):4x, 8x, 16x and 32x complex decimationFour independent 32-Bit NCOs per DDCPeak RF Input Power (Diff): +26.5dBm (+ 27.5dBFS, 560x fullscale power)Programmable FIR filter for equalizationPower consumption: 3.7WPower supplies: 1.1V, 1.9VADC core:12-bit resolutionUp to 8GSPS in single-channel modeUp to 4GSPS in dual-channel modePerformance specifications:Noise floor (–20dBFS, VFS = 1VPP-DIFF):Dual-channel mode: –152.3dBFS/HzSingle-channel mode: –155dBFS/HzENOB (dual channel, FIN = 2.4GHz): 8.8 BitsBuffered analog inputs with VCMI of 0 V:Analog input bandwidth (–3dB): 8GHzUsable input frequency range: > 10GHzFull-scale input voltage (VFS, default): 0.8VPPNoiseless aperture delay (tAD) adjustment:Precise sampling control: 19fs StepSimplifies synchronization and interleavingTemperature and voltage invariant delaysEasy-to-use synchronization features:Automatic SYSREF timing calibrationTimestamp for sample markingJESD204C serial data interface:Maximum lane rate: 17.16GbpsSupport for 64b/66b and 8b/10b encoding8b/10b modes are JESD204B compatibleOptional digital down-converters (DDC):4x, 8x, 16x and 32x complex decimationFour independent 32-Bit NCOs per DDCPeak RF Input Power (Diff): +26.5dBm (+ 27.5dBFS, 560x fullscale power)Programmable FIR filter for equalizationPower consumption: 3.7WPower supplies: 1.1V, 1.9V

Description

AI
The ADC12DJ4000RF device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. ADC12DJ4000RF can be configured as a dual-channel, 4 GSPS ADC or single-channel, 8 GSPS ADC. Support of a useable input frequency range of up to 10GHz enables direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems. The ADC12DJ4000RF uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers. Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multi-channel applications. Optional digital down converters (DDCs) are available to provide digital conversion to baseband and to reduce the interface rate. A programmable FIR filter allows on-chip equalization. The ADC12DJ4000RF device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. ADC12DJ4000RF can be configured as a dual-channel, 4 GSPS ADC or single-channel, 8 GSPS ADC. Support of a useable input frequency range of up to 10GHz enables direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems. The ADC12DJ4000RF uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers. Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multi-channel applications. Optional digital down converters (DDCs) are available to provide digital conversion to baseband and to reduce the interface rate. A programmable FIR filter allows on-chip equalization.