Integrated Circuits (ICs)

SN74LVT574DWR

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3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

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Search across all available documentation for this part.

DocumentsTI IBIS File Creation, Validation, and Distribution Processes Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)+15

Integrated Circuits (ICs)

SN74LVT574DWR

Active

Texas Instruments

3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

Deep-Dive with AI

DocumentsTI IBIS File Creation, Validation, and Distribution Processes Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)+15

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	SN74LVT574DWR

Clock Frequency	150 MHz
Current - Output High, Low [custom]	64 mA
Current - Output High, Low [custom]	32 mA
Current - Quiescent (Iq)	190 çA
Function	Standard
Input Capacitance	4 pF
Max Propagation Delay @ V, Max CL	5.9 ns
Mounting Type	Surface Mount
Number of Bits per Element	8
Number of Elements	1
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output Type	Tri-State, Non-Inverted
Package / Case	20-SOIC
Package / Case [y]	0.295 in
Package / Case [y]	7.5 mm
Supplier Device Package	20-SOIC
Trigger Type	Positive Edge
Type	D-Type
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	2.7 V

SN74LVT574 Series

3.3-V ABT Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs

Part	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Input Capacitance	Current - Quiescent (Iq)	Number of Bits per Element	Clock Frequency	Trigger Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Function	Supplier Device Package	Output Type	Number of Elements	Operating Temperature [Max]	Operating Temperature [Min]	Max Propagation Delay @ V, Max CL	Mounting Type	Type	Package / Case	Package / Case [y]	Package / Case [y]	Package / Case [x]
Texas Instruments SN74LVT574DW	64 mA	32 mA	4 pF	190 çA	8	150 MHz	Positive Edge	2.7 V	3.6 V	Standard	20-SOIC	Non-Inverted Tri-State	1	85 °C	-40 °C	5.9 ns	Surface Mount	D-Type	20-SOIC	0.295 in	7.5 mm
Texas Instruments SN74LVT574PWR	64 mA	32 mA	4 pF	190 çA	8	150 MHz	Positive Edge	2.7 V	3.6 V	Standard	20-TSSOP	Non-Inverted Tri-State	1	85 °C	-40 °C	6.6 ns	Surface Mount	D-Type	20-TSSOP	4.4 mm		0.173 in
Texas Instruments SN74LVT574DWR	64 mA	32 mA	4 pF	190 çA	8	150 MHz	Positive Edge	2.7 V	3.6 V	Standard	20-SOIC	Non-Inverted Tri-State	1	85 °C	-40 °C	5.9 ns	Surface Mount	D-Type	20-SOIC	0.295 in	7.5 mm
Texas Instruments SN74LVT574DBR	64 mA	32 mA	4 pF	190 çA	8	150 MHz	Positive Edge	2.7 V	3.6 V	Standard	20-SSOP	Non-Inverted Tri-State	1	85 °C	-40 °C	6.6 ns	Surface Mount	D-Type	20-SSOP

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Cut Tape (CT)	1	$ 3.55
		10	$ 2.32
		25	$ 2.00
		100	$ 1.64
		250	$ 1.47
		500	$ 1.36
		1000	$ 1.27
	Digi-Reel®	1	$ 3.55
		10	$ 2.32
		25	$ 2.00
		100	$ 1.64
		250	$ 1.47
		500	$ 1.36
		1000	$ 1.27
	Tape & Reel (TR)	2000	$ 1.20
		4000	$ 1.14
		6000	$ 1.11
Texas Instruments	LARGE T&R	1	$ 1.95
		100	$ 1.61
		250	$ 1.16
		1000	$ 0.87

Description

General part information

SN74LVT574 Series

These octal flip-flops are designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment.

The eight flip-flops of the ´LVT574 are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.

A buffered output-enableinput can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.