SN74LVT574PWR
Active3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
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SN74LVT574PWR
Active3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
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Technical Specifications
Parameters and characteristics for this part
| Specification | SN74LVT574PWR |
|---|---|
| Clock Frequency | 150 MHz |
| Current - Output High, Low [custom] | 64 mA |
| Current - Output High, Low [custom] | 32 mA |
| Current - Quiescent (Iq) | 190 çA |
| Function | Standard |
| Input Capacitance | 4 pF |
| Max Propagation Delay @ V, Max CL | 6.6 ns |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 8 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Tri-State, Non-Inverted |
| Package / Case | 20-TSSOP |
| Package / Case [x] | 0.173 in |
| Package / Case [y] | 4.4 mm |
| Supplier Device Package | 20-TSSOP |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 2.7 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 2.59 | |
| 10 | $ 2.33 | |||
| 25 | $ 2.19 | |||
| 100 | $ 1.87 | |||
| 250 | $ 1.76 | |||
| 500 | $ 1.54 | |||
| 1000 | $ 1.27 | |||
| Digi-Reel® | 1 | $ 2.59 | ||
| 10 | $ 2.33 | |||
| 25 | $ 2.19 | |||
| 100 | $ 1.87 | |||
| 250 | $ 1.76 | |||
| 500 | $ 1.54 | |||
| 1000 | $ 1.27 | |||
| Tape & Reel (TR) | 2000 | $ 1.09 | ||
| Texas Instruments | LARGE T&R | 1 | $ 1.95 | |
| 100 | $ 1.61 | |||
| 250 | $ 1.16 | |||
| 1000 | $ 0.87 | |||
Description
General part information
SN74LVT574 Series
These octal flip-flops are designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment.
The eight flip-flops of the ´LVT574 are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.
A buffered output-enableinput can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
Documents
Technical documentation and resources
