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DFN-S / 8
Integrated Circuits (ICs)

TC4423AVMF

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Microchip Technology

MOSFET DRVR 4.5A 2-OUT LO SIDE INV 8-PIN DFN-S EP TUBE

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DFN-S / 8
Integrated Circuits (ICs)

TC4423AVMF

Active
Microchip Technology

MOSFET DRVR 4.5A 2-OUT LO SIDE INV 8-PIN DFN-S EP TUBE

Technical Specifications

Parameters and characteristics for this part

SpecificationTC4423AVMF
Channel TypeIndependent
Current - Peak Output (Source, Sink) [custom]4.5 A
Current - Peak Output (Source, Sink) [custom]4.5 A
Driven ConfigurationLow-Side
Gate TypeN-Channel, P-Channel MOSFET
Input TypeInverting
Mounting TypeSurface Mount
Number of Drivers2
Operating Temperature [Max]150 °C
Operating Temperature [Min]-40 °C
Package / Case8-VDFN Exposed Pad
Rise / Fall Time (Typ)12 ns
Rise / Fall Time (Typ)12 ns
Supplier Device Package8-DFN-S (6x5)
Voltage - Supply [Max]18 V
Voltage - Supply [Min]4.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 240$ 1.86
Microchip DirectTUBE 1$ 2.45
25$ 2.04
100$ 1.86
1000$ 1.80
5000$ 1.77

Description

General part information

TC4423A Series

The TC4423/4424/4425 are higher output current versions of the new TC4426/4427/4428 buffer/gate drivers which, in turn, are improved versions of the earlier TC426/427/428 series. All three families are pin-compatible. The TC4423/4424/4425 gate drivers are capable of giving reliable service in far more demanding electrical environments than their antecedents. Although primarily intended for driving power MOSFETs, the TC4423/4424/4425 gate drivers are equally well-suited to driving any other load (capacitive, resistive, or inductive) which requires a low impedance driver capable of high peak currents and fast switching times. For example, heavily loaded clock lines, coaxial cables, or piezoelectric transducers can all be driven from the TC4423/4424/4425. The only known limitation on loading is the total power dissipated in the driver must be kept within the maximum power dissipation limits of the package.