Integrated Circuits (ICs)

CD74AC373M96

Active

LATCH TRANSPARENT 3-ST 8-CH D-TYPE 20-PIN SOIC T/R

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Search across all available documentation for this part.

DocumentsUsing High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Power-Up Behavior of Clocked Devices (Rev. B)+12

Integrated Circuits (ICs)

CD74AC373M96

Active

Texas Instruments

LATCH TRANSPARENT 3-ST 8-CH D-TYPE 20-PIN SOIC T/R

Deep-Dive with AI

DocumentsUsing High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Power-Up Behavior of Clocked Devices (Rev. B)+12

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	CD74AC373M96

Circuit [custom]	8
Circuit [custom]	8
Current - Output High, Low	24 mA
Delay Time - Propagation	3 ns
Independent Circuits	1
Logic Type	D-Type Transparent Latch
Mounting Type	Surface Mount
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-55 °C
Output Type	Tri-State
Package / Case	20-SOIC
Package / Case [y]	0.295 in
Package / Case [y]	7.5 mm
Supplier Device Package	20-SOIC
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	1.5 V

SN74AC373-EP Series

Enhanced Product Octal D-Type Transparent Latches With 3-State Outputs

Part	Voltage - Supply [Min]	Voltage - Supply [Max]	Supplier Device Package	Delay Time - Propagation	Operating Temperature [Max]	Operating Temperature [Min]	Mounting Type	Circuit [custom]	Circuit [custom]	Output Type	Current - Output High, Low	Logic Type	Package / Case	Package / Case [y]	Package / Case [y]	Independent Circuits	Package / Case [x]	Package / Case	Package / Case
Texas Instruments SN74AC373DW	2 V	6 V	20-SOIC	7.5 ns	85 °C	-40 °C	Surface Mount	8	8	Tri-State	24 mA	D-Type Transparent Latch	20-SOIC	0.295 in	7.5 mm	1
Texas Instruments SN74AC373PW	2 V	6 V	20-TSSOP	7.5 ns	85 °C	-40 °C	Surface Mount	8	8	Tri-State	24 mA	D-Type Transparent Latch	20-TSSOP	4.4 mm		1	0.173 in
Texas Instruments SN74AC373NSR	2 V	6 V	20-SO	7.5 ns	85 °C	-40 °C	Surface Mount	8	8	Tri-State	24 mA	D-Type Transparent Latch	20-SOIC			1		0.209 "	5.3 mm
Texas Instruments CD74AC373E	1.5 V	5.5 V	20-PDIP	3 ns	125 °C	-55 °C	Through Hole	8	8	Tri-State	24 mA	D-Type Transparent Latch	20-DIP			1		0.3 in	7.62 mm
Texas Instruments CD74AC373M96	1.5 V	5.5 V	20-SOIC	3 ns	125 °C	-55 °C	Surface Mount	8	8	Tri-State	24 mA	D-Type Transparent Latch	20-SOIC	0.295 in	7.5 mm	1
Texas Instruments SN74AC373DBR	2 V	6 V	20-SSOP	7.5 ns	85 °C	-40 °C	Surface Mount	8	8	Tri-State	24 mA	D-Type Transparent Latch	20-SSOP			1
Texas Instruments CD74AC373M	1.5 V	5.5 V	20-SOIC	3 ns	125 °C	-55 °C	Surface Mount	8	8	Tri-State	24 mA	D-Type Transparent Latch	20-SOIC	0.295 in	7.5 mm	1
Texas Instruments SN74AC373NG4	2 V	6 V	20-PDIP	7.5 ns	85 °C	-40 °C	Through Hole	8	8	Tri-State	24 mA	D-Type Transparent Latch	20-DIP			1		0.3 in	7.62 mm
Texas Instruments SN74AC373DWR	2 V	6 V	20-SOIC	7.5 ns	85 °C	-40 °C	Surface Mount	8	8	Tri-State	24 mA	D-Type Transparent Latch	20-SOIC	0.295 in	7.5 mm	1
Texas Instruments SN74AC373MDWREP	2 V	6 V	20-SOIC	7.5 ns	125 °C	-55 °C	Surface Mount	8	8	Tri-State	24 mA	D-Type Transparent Latch	20-SOIC	0.295 in	7.5 mm	1

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Cut Tape (CT)	1	$ 0.87
		10	$ 0.78
		25	$ 0.74
		100	$ 0.61
	Digi-Reel®	1	$ 0.87
		10	$ 0.78
		25	$ 0.74
		100	$ 0.61
	Tape & Reel (TR)	2000	$ 0.32
		6000	$ 0.30
		10000	$ 0.29
Texas Instruments	LARGE T&R	1	$ 0.55
		100	$ 0.42
		250	$ 0.31
		1000	$ 0.22

Description

General part information

SN74AC373-EP Series

This 8-bit latch features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight latches are D-type transparent latches. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines in bus-organized systems without need for interface or pullup components.

Documents

Technical documentation and resources

CD74AC373M96

Deep-Dive with AI

CD74AC373M96

Deep-Dive with AI

Technical Specifications

SN74AC373-EP Series

Pricing

Description

SN74AC373-EP Series

Documents

Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc

Power-Up Behavior of Clocked Devices (Rev. B)

CMOS Power Consumption and CPD Calculation (Rev. B)

CDx4AC373, CDx4ACT373 Octal Transparent Latch, 3-State datasheet (Rev. A)

TI IBIS File Creation, Validation, and Distribution Processes

Implications of Slow or Floating CMOS Inputs (Rev. E)

Input and Output Characteristics of Digital Integrated Circuits

Logic Guide (Rev. AB)

Designing With Logic (Rev. C)

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Live Insertion

HiRel Unitrode Power Management Brochure

LOGIC Pocket Data Book (Rev. B)

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

SN74AC373-EP Series