
CD74AC373E
ActiveLATCH TRANSPARENT 3-ST 8-CH D-TYPE 20-PIN PDIP TUBE
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CD74AC373E
ActiveLATCH TRANSPARENT 3-ST 8-CH D-TYPE 20-PIN PDIP TUBE
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Technical Specifications
Parameters and characteristics for this part
| Specification | CD74AC373E |
|---|---|
| Circuit [custom] | 8 |
| Circuit [custom] | 8 |
| Current - Output High, Low | 24 mA |
| Delay Time - Propagation | 3 ns |
| Independent Circuits | 1 |
| Logic Type | D-Type Transparent Latch |
| Mounting Type | Through Hole |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Output Type | Tri-State |
| Package / Case | 20-DIP |
| Package / Case | 7.62 mm |
| Package / Case | 0.3 in |
| Supplier Device Package | 20-PDIP |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 1.5 V |
SN74AC373-EP Series
Enhanced Product Octal D-Type Transparent Latches With 3-State Outputs
| Part | Voltage - Supply [Min] | Voltage - Supply [Max] | Supplier Device Package | Delay Time - Propagation | Operating Temperature [Max] | Operating Temperature [Min] | Mounting Type | Circuit [custom] | Circuit [custom] | Output Type | Current - Output High, Low | Logic Type | Package / Case | Package / Case [y] | Package / Case [y] | Independent Circuits | Package / Case [x] | Package / Case | Package / Case |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments | 2 V | 6 V | 20-SOIC | 7.5 ns | 85 °C | -40 °C | Surface Mount | 8 | 8 | Tri-State | 24 mA | D-Type Transparent Latch | 20-SOIC | 0.295 in | 7.5 mm | 1 | |||
Texas Instruments | 2 V | 6 V | 20-TSSOP | 7.5 ns | 85 °C | -40 °C | Surface Mount | 8 | 8 | Tri-State | 24 mA | D-Type Transparent Latch | 20-TSSOP | 4.4 mm | 1 | 0.173 in | |||
Texas Instruments | 2 V | 6 V | 20-SO | 7.5 ns | 85 °C | -40 °C | Surface Mount | 8 | 8 | Tri-State | 24 mA | D-Type Transparent Latch | 20-SOIC | 1 | 0.209 " | 5.3 mm | |||
Texas Instruments | 1.5 V | 5.5 V | 20-PDIP | 3 ns | 125 °C | -55 °C | Through Hole | 8 | 8 | Tri-State | 24 mA | D-Type Transparent Latch | 20-DIP | 1 | 0.3 in | 7.62 mm | |||
Texas Instruments | 1.5 V | 5.5 V | 20-SOIC | 3 ns | 125 °C | -55 °C | Surface Mount | 8 | 8 | Tri-State | 24 mA | D-Type Transparent Latch | 20-SOIC | 0.295 in | 7.5 mm | 1 | |||
Texas Instruments | 2 V | 6 V | 20-SSOP | 7.5 ns | 85 °C | -40 °C | Surface Mount | 8 | 8 | Tri-State | 24 mA | D-Type Transparent Latch | 20-SSOP | 1 | |||||
Texas Instruments | 1.5 V | 5.5 V | 20-SOIC | 3 ns | 125 °C | -55 °C | Surface Mount | 8 | 8 | Tri-State | 24 mA | D-Type Transparent Latch | 20-SOIC | 0.295 in | 7.5 mm | 1 | |||
Texas Instruments | 2 V | 6 V | 20-PDIP | 7.5 ns | 85 °C | -40 °C | Through Hole | 8 | 8 | Tri-State | 24 mA | D-Type Transparent Latch | 20-DIP | 1 | 0.3 in | 7.62 mm | |||
Texas Instruments | 2 V | 6 V | 20-SOIC | 7.5 ns | 85 °C | -40 °C | Surface Mount | 8 | 8 | Tri-State | 24 mA | D-Type Transparent Latch | 20-SOIC | 0.295 in | 7.5 mm | 1 | |||
Texas Instruments | 2 V | 6 V | 20-SOIC | 7.5 ns | 125 °C | -55 °C | Surface Mount | 8 | 8 | Tri-State | 24 mA | D-Type Transparent Latch | 20-SOIC | 0.295 in | 7.5 mm | 1 |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Arrow | N/A | 20 | $ 0.83 | |
| 40 | $ 0.83 | |||
| 100 | $ 0.81 | |||
| 260 | $ 0.76 | |||
| 500 | $ 0.75 | |||
| Digikey | Tube | 1 | $ 1.99 | |
| 20 | $ 1.78 | |||
| 40 | $ 1.68 | |||
| 100 | $ 1.43 | |||
| 260 | $ 1.35 | |||
| 333 | $ 0.90 | |||
| 500 | $ 1.18 | |||
| 1000 | $ 0.98 | |||
| 2500 | $ 0.91 | |||
| 5000 | $ 0.88 | |||
| Texas Instruments | TUBE | 1 | $ 1.67 | |
| 100 | $ 1.28 | |||
| 250 | $ 0.94 | |||
| 1000 | $ 0.68 | |||
Description
General part information
SN74AC373-EP Series
This 8-bit latch features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight latches are D-type transparent latches. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.
A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines in bus-organized systems without need for interface or pullup components.
Documents
Technical documentation and resources