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Texas Instruments-CD74FCT244ATE Buffers and Line Drivers Buffer/Line Driver 8-CH Non-Inverting 3-ST CMOS 20-Pin PDIP Tube
Integrated Circuits (ICs)

CD74AC373E

Active
Texas Instruments

LATCH TRANSPARENT 3-ST 8-CH D-TYPE 20-PIN PDIP TUBE

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Texas Instruments-CD74FCT244ATE Buffers and Line Drivers Buffer/Line Driver 8-CH Non-Inverting 3-ST CMOS 20-Pin PDIP Tube
Integrated Circuits (ICs)

CD74AC373E

Active
Texas Instruments

LATCH TRANSPARENT 3-ST 8-CH D-TYPE 20-PIN PDIP TUBE

Technical Specifications

Parameters and characteristics for this part

SpecificationCD74AC373E
Circuit [custom]8
Circuit [custom]8
Current - Output High, Low24 mA
Delay Time - Propagation3 ns
Independent Circuits1
Logic TypeD-Type Transparent Latch
Mounting TypeThrough Hole
Operating Temperature [Max]125 °C
Operating Temperature [Min]-55 °C
Output TypeTri-State
Package / Case20-DIP
Package / Case7.62 mm
Package / Case0.3 in
Supplier Device Package20-PDIP
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]1.5 V

SN74AC373-EP Series

Enhanced Product Octal D-Type Transparent Latches With 3-State Outputs

PartVoltage - Supply [Min]Voltage - Supply [Max]Supplier Device PackageDelay Time - PropagationOperating Temperature [Max]Operating Temperature [Min]Mounting TypeCircuit [custom]Circuit [custom]Output TypeCurrent - Output High, LowLogic TypePackage / CasePackage / Case [y]Package / Case [y]Independent CircuitsPackage / Case [x]Package / CasePackage / Case
SOIC (DW)
Texas Instruments
2 V
6 V
20-SOIC
7.5 ns
85 °C
-40 °C
Surface Mount
8
8
Tri-State
24 mA
D-Type Transparent Latch
20-SOIC
0.295 in
7.5 mm
1
20-TSSOP
Texas Instruments
2 V
6 V
20-TSSOP
7.5 ns
85 °C
-40 °C
Surface Mount
8
8
Tri-State
24 mA
D-Type Transparent Latch
20-TSSOP
4.4 mm
1
0.173 in
SOP (NS)
Texas Instruments
2 V
6 V
20-SO
7.5 ns
85 °C
-40 °C
Surface Mount
8
8
Tri-State
24 mA
D-Type Transparent Latch
20-SOIC
1
0.209 "
5.3 mm
Texas Instruments-CD74FCT244ATE Buffers and Line Drivers Buffer/Line Driver 8-CH Non-Inverting 3-ST CMOS 20-Pin PDIP Tube
Texas Instruments
1.5 V
5.5 V
20-PDIP
3 ns
125 °C
-55 °C
Through Hole
8
8
Tri-State
24 mA
D-Type Transparent Latch
20-DIP
1
0.3 in
7.62 mm
20-SOIC
Texas Instruments
1.5 V
5.5 V
20-SOIC
3 ns
125 °C
-55 °C
Surface Mount
8
8
Tri-State
24 mA
D-Type Transparent Latch
20-SOIC
0.295 in
7.5 mm
1
SSOP (DB)
Texas Instruments
2 V
6 V
20-SSOP
7.5 ns
85 °C
-40 °C
Surface Mount
8
8
Tri-State
24 mA
D-Type Transparent Latch
20-SSOP
1
SOIC (DW)
Texas Instruments
1.5 V
5.5 V
20-SOIC
3 ns
125 °C
-55 °C
Surface Mount
8
8
Tri-State
24 mA
D-Type Transparent Latch
20-SOIC
0.295 in
7.5 mm
1
20-DIP
Texas Instruments
2 V
6 V
20-PDIP
7.5 ns
85 °C
-40 °C
Through Hole
8
8
Tri-State
24 mA
D-Type Transparent Latch
20-DIP
1
0.3 in
7.62 mm
20-SOIC,DW
Texas Instruments
2 V
6 V
20-SOIC
7.5 ns
85 °C
-40 °C
Surface Mount
8
8
Tri-State
24 mA
D-Type Transparent Latch
20-SOIC
0.295 in
7.5 mm
1
SOIC (DW)
Texas Instruments
2 V
6 V
20-SOIC
7.5 ns
125 °C
-55 °C
Surface Mount
8
8
Tri-State
24 mA
D-Type Transparent Latch
20-SOIC
0.295 in
7.5 mm
1

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
ArrowN/A 20$ 0.83
40$ 0.83
100$ 0.81
260$ 0.76
500$ 0.75
DigikeyTube 1$ 1.99
20$ 1.78
40$ 1.68
100$ 1.43
260$ 1.35
333$ 0.90
500$ 1.18
1000$ 0.98
2500$ 0.91
5000$ 0.88
Texas InstrumentsTUBE 1$ 1.67
100$ 1.28
250$ 0.94
1000$ 0.68

Description

General part information

SN74AC373-EP Series

This 8-bit latch features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight latches are D-type transparent latches. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines in bus-organized systems without need for interface or pullup components.