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14-SOIC
Integrated Circuits (ICs)

CD4086BMT

Active
Texas Instruments

AND-OR-INVERT GATE 1-ELEMENT 4 WIDE 2-IN CMOS 14-PIN SOIC T/R

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14-SOIC
Integrated Circuits (ICs)

CD4086BMT

Active
Texas Instruments

AND-OR-INVERT GATE 1-ELEMENT 4 WIDE 2-IN CMOS 14-PIN SOIC T/R

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationCD4086BMT
Current - Output High, Low [custom]6.8 mA
Current - Output High, Low [custom]6.8 mA
Logic TypeINVERT Gate, OR, AND
Mounting TypeSurface Mount
Number of Circuits1
Number of Inputs8 Input
Operating Temperature [Max]125 °C
Operating Temperature [Min]-55 °C
Output TypeSingle-Ended
Package / Case14-SOIC
Package / Case [x]0.154 in
Package / Case [y]3.9 mm
Schmitt Trigger InputFalse
Voltage - Supply [Max]18 V
Voltage - Supply [Min]3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
ArrowN/A 250$ 0.65
DigikeyCut Tape (CT) 1$ 0.63
10$ 0.54
25$ 0.51
100$ 0.40
Digi-Reel® 1$ 0.95
10$ 0.59
25$ 0.50
100$ 0.39
Tape & Reel (TR) 250$ 0.38
500$ 0.32
1250$ 0.25
2500$ 0.22
6250$ 0.21
12500$ 0.19
25000$ 0.18
Texas InstrumentsSMALL T&R 1$ 0.47
100$ 0.32
250$ 0.25
1000$ 0.16

Description

General part information

CD4086B Series

CD4086B contains one 4-wide 2-input AND-OR-INVERT gate with an INHIBIT/(EXP\) input and an ENABLE/EXP input. For a 4-wide A-O-I function INHIBIT/(EXP\) is tied to VSSand ENABLE/EXP to VDD. See Fig. 10 and its associated explanation for applications where a capability greater than 4-wide is required.

The CD4086B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4086B contains one 4-wide 2-input AND-OR-INVERT gate with an INHIBIT/(EXP\) input and an ENABLE/EXP input. For a 4-wide A-O-I function INHIBIT/(EXP\) is tied to VSSand ENABLE/EXP to VDD. See Fig. 10 and its associated explanation for applications where a capability greater than 4-wide is required.

Documents

Technical documentation and resources