CD4086B Series

CMOS Expandable 4-Wide 2-Input AND-OR-INVERT Gate

Catalog

CMOS Expandable 4-Wide 2-Input AND-OR-INVERT Gate

Part	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Package / Case	Package / Case [y]	Package / Case [x]	Mounting Type	Number of Inputs	Operating Temperature [Min]	Operating Temperature [Max]	Number of Circuits	Logic Type	Output Type	Voltage - Supply [Max]	Voltage - Supply [Min]	Package / Case [custom]	Package / Case [custom]	Supplier Device Package
Texas Instruments CD4086BEE4	6.8 mA	6.8 mA	14-DIP	7.62 mm	0.3 "	Through Hole	8 Input	-55 °C	125 °C	1	AND INVERT Gate OR	Single-Ended	18 V	3 V
Texas Instruments CD4086BM96	6.8 mA	6.8 mA	14-SOIC	3.9 mm	0.154 in	Surface Mount	8 Input	-55 °C	125 °C	1	AND INVERT Gate OR	Single-Ended	18 V	3 V
Texas Instruments CD4086BM	6.8 mA	6.8 mA	14-SOIC	3.9 mm	0.154 in	Surface Mount	8 Input	-55 °C	125 °C	1	AND INVERT Gate OR	Single-Ended	18 V	3 V
Texas Instruments CD4086BM96G4	6.8 mA	6.8 mA	14-SOIC	3.9 mm	0.154 in	Surface Mount	8 Input	-55 °C	125 °C	1	AND INVERT Gate OR	Single-Ended	18 V	3 V
Texas Instruments CD4086BPWR	6.8 mA	6.8 mA	14-TSSOP			Surface Mount	8 Input	-55 °C	125 °C	1	AND INVERT Gate OR	Single-Ended	18 V	3 V	0.173 "	4.4 mm	14-TSSOP
Texas Instruments CD4086BMT	6.8 mA	6.8 mA	14-SOIC	3.9 mm	0.154 in	Surface Mount	8 Input	-55 °C	125 °C	1	AND INVERT Gate OR	Single-Ended	18 V	3 V
Texas Instruments CD4086BM96E4	6.8 mA	6.8 mA	14-SOIC	3.9 mm	0.154 in	Surface Mount	8 Input	-55 °C	125 °C	1	AND INVERT Gate OR	Single-Ended	18 V	3 V
Texas Instruments CD4086BME4	6.8 mA	6.8 mA	14-SOIC	3.9 mm	0.154 in	Surface Mount	8 Input	-55 °C	125 °C	1	AND INVERT Gate OR	Single-Ended	18 V	3 V

Catalog

CMOS Expandable 4-Wide 2-Input AND-OR-INVERT Gate

Key Features

• Medium-speed operation - tPHL= 90 ns; tPLH= 140 ns (typ.) at 10 VINHIBIT and ENABLE inputsBuffered outputs100% tested for quiescent current at 20 VMaximum input leakage current of 18 V over full package-temperature range; 100 nA at 18 V and 25°CNoise margin (over full package temperature range):1 V at VDD= 5 V2 V at VDD= 10 V2.5 V at VDD= 15 VStandardized, symmetrical output characteristics5-V, 10-V, and 15-V parametric ratingsMeets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"Medium-speed operation - tPHL= 90 ns; tPLH= 140 ns (typ.) at 10 VINHIBIT and ENABLE inputsBuffered outputs100% tested for quiescent current at 20 VMaximum input leakage current of 18 V over full package-temperature range; 100 nA at 18 V and 25°CNoise margin (over full package temperature range):1 V at VDD= 5 V2 V at VDD= 10 V2.5 V at VDD= 15 VStandardized, symmetrical output characteristics5-V, 10-V, and 15-V parametric ratingsMeets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"

Description

CD4086B contains one 4-wide 2-input AND-OR-INVERT gate with an INHIBIT/(EXP\) input and an ENABLE/EXP input. For a 4-wide A-O-I function INHIBIT/(EXP\) is tied to VSSand ENABLE/EXP to VDD. See Fig. 10 and its associated explanation for applications where a capability greater than 4-wide is required. The CD4086B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes). CD4086B contains one 4-wide 2-input AND-OR-INVERT gate with an INHIBIT/(EXP\) input and an ENABLE/EXP input. For a 4-wide A-O-I function INHIBIT/(EXP\) is tied to VSSand ENABLE/EXP to VDD. See Fig. 10 and its associated explanation for applications where a capability greater than 4-wide is required. The CD4086B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).