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Technical Specifications
Parameters and characteristics for this part
| Specification | CD4086BM96 |
|---|---|
| Current - Output High, Low [custom] | 6.8 mA |
| Current - Output High, Low [custom] | 6.8 mA |
| Logic Type | INVERT Gate, OR, AND |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Number of Inputs | 8 Input |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Output Type | Single-Ended |
| Package / Case | 14-SOIC |
| Package / Case [x] | 0.154 in |
| Package / Case [y] | 3.9 mm |
| Schmitt Trigger Input | False |
| Voltage - Supply [Max] | 18 V |
| Voltage - Supply [Min] | 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
Description
General part information
CD4086B Series
CD4086B contains one 4-wide 2-input AND-OR-INVERT gate with an INHIBIT/(EXP\) input and an ENABLE/EXP input. For a 4-wide A-O-I function INHIBIT/(EXP\) is tied to VSSand ENABLE/EXP to VDD. See Fig. 10 and its associated explanation for applications where a capability greater than 4-wide is required.
The CD4086B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).
CD4086B contains one 4-wide 2-input AND-OR-INVERT gate with an INHIBIT/(EXP\) input and an ENABLE/EXP input. For a 4-wide A-O-I function INHIBIT/(EXP\) is tied to VSSand ENABLE/EXP to VDD. See Fig. 10 and its associated explanation for applications where a capability greater than 4-wide is required.
Documents
Technical documentation and resources
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