Deep-Dive with AI
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Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | 74ACT11286N |
|---|---|
| Current - Output High, Low [custom] | 24 mA |
| Current - Output High, Low [custom] | 24 mA |
| Logic Type | Parity Generator/Checker |
| Mounting Type | Through Hole |
| Number of Circuits | 9-Bit |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 C |
| Package / Case | 14-DIP |
| Package / Case | 0.3 in |
| Package / Case | 7.62 mm |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 4.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | N/A | 0 | $ 1.85 | |
| 12300 | $ 1.85 | |||
Description
General part information
74ACT11286 Series
The 74ACT11286 universal 9-bit parity generator/checker features a local output for parity checking and a bus-driving parity I/O port for parity generation/checking. The word-length capability is easily expanded by cascading.
Thecontrol input is implemented specifically to accommodate cascading. When theis low, the parity tree is disabled and the PARITY ERROR output remains at a high logic level, regardless of the input levels. Whenis high, the parity tree is enabled. PARITY ERROR indicates a parity error when either an even number of inputs (A through I) are high and PARITY I/O is forced to a low logic level, or when an odd number of inputs are high and PARITY I/O is forced to a high logic level.
The I/O control circuitry is designed so that the I/O port remains in the high-impedance state during power up or power down, to prevent bus glitches.
Documents
Technical documentation and resources
