Specification	74ACT11286D

Current - Output High, Low [custom]	24 mA
Current - Output High, Low [custom]	24 mA
Logic Type	Parity Generator/Checker
Mounting Type	Surface Mount
Number of Circuits	9-Bit
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 C
Package / Case	3.9 mm, 0.154 in
Package / Case	14-SOIC
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	4.5 V

74ACT11286 Series

9-Bit Parity Generators/Checkers With Bus Driver Parity I/O Ports

Part	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Mounting Type	Logic Type	Package / Case	Package / Case	Voltage - Supply [Min]	Voltage - Supply [Max]	Number of Circuits	Operating Temperature [Max]	Operating Temperature [Min]	Package / Case	Package / Case
Texas Instruments 74ACT11286D	24 mA	24 mA	Surface Mount	Parity Generator/Checker	0.154 in 3.9 mm	14-SOIC	4.5 V	5.5 V	9-Bit	85 °C	-40 C
Texas Instruments 74ACT11286DR	24 mA	24 mA	Surface Mount	Parity Generator/Checker	0.154 in 3.9 mm	14-SOIC	4.5 V	5.5 V	9-Bit	85 °C	-40 C
Texas Instruments 74ACT11286N	24 mA	24 mA	Through Hole	Parity Generator/Checker		14-DIP	4.5 V	5.5 V	9-Bit	85 °C	-40 C	0.3 in	7.62 mm

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	N/A	0	$ 3.14
		15289	$ 3.14
Texas Instruments	TUBE	1	$ 3.79
		100	$ 3.32
		250	$ 2.33
		1000	$ 1.88

Description

General part information

74ACT11286 Series

The 74ACT11286 universal 9-bit parity generator/checker features a local output for parity checking and a bus-driving parity I/O port for parity generation/checking. The word-length capability is easily expanded by cascading.

Thecontrol input is implemented specifically to accommodate cascading. When theis low, the parity tree is disabled and the PARITY ERROR output remains at a high logic level, regardless of the input levels. Whenis high, the parity tree is enabled. PARITY ERROR indicates a parity error when either an even number of inputs (A through I) are high and PARITY I/O is forced to a low logic level, or when an odd number of inputs are high and PARITY I/O is forced to a high logic level.

The I/O control circuitry is designed so that the I/O port remains in the high-impedance state during power up or power down, to prevent bus glitches.

Documents

Technical documentation and resources

9-Bit Parity Generator/Checker With Bus Driver Parity I/O Ports datasheet (Rev. B)

Data sheet