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16-TSSOP
Integrated Circuits (ICs)

CD4044BPWR

Active
Texas Instruments

CMOS QUAD NAND R/S LATCH WITH 3-STATE OUTPUTS

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16-TSSOP
Integrated Circuits (ICs)

CD4044BPWR

Active
Texas Instruments

CMOS QUAD NAND R/S LATCH WITH 3-STATE OUTPUTS

Technical Specifications

Parameters and characteristics for this part

SpecificationCD4044BPWR
Circuit1:1
Current - Output High, Low [custom]6.8 mA
Current - Output High, Low [custom]6.8 mA
Delay Time - Propagation50 ns
Independent Circuits4
Logic TypeS-R Latch
Mounting TypeSurface Mount
Operating Temperature [Max]125 °C
Operating Temperature [Min]-55 °C
Output TypeTri-State
Package / Case16-TSSOP
Package / Case [x]0.173 in
Package / Case [y]4.4 mm
Supplier Device Package16-TSSOP
Voltage - Supply [Max]18 V
Voltage - Supply [Min]3 V

CD4044B Series

CMOS Quad NAND R/S Latch with 3-State Outputs

PartSupplier Device PackageLogic TypeCircuitCurrent - Output High, Low [custom]Current - Output High, Low [custom]Mounting TypeDelay Time - PropagationVoltage - Supply [Max]Voltage - Supply [Min]Output TypeOperating Temperature [Min]Operating Temperature [Max]Independent CircuitsPackage / Case [x]Package / CasePackage / Case [y]Package / CasePackage / Case
16-SOIC
Texas Instruments
16-SOIC
S-R Latch
1:1
6.8 mA
6.8 mA
Surface Mount
50 ns
18 V
3 V
Tri-State
-55 °C
125 °C
4
0.295 in
16-SOIC
7.5 mm
16-SOIC
Texas Instruments
16-SOIC
S-R Latch
1:1
6.8 mA
6.8 mA
Surface Mount
50 ns
18 V
3 V
Tri-State
-55 °C
125 °C
4
0.295 in
16-SOIC
7.5 mm
SOIC (D)
Texas Instruments
16-SOIC
S-R Latch
1:1
6.8 mA
6.8 mA
Surface Mount
50 ns
18 V
3 V
Tri-State
-55 °C
125 °C
4
0.154 in
16-SOIC
3.9 mm
SOIC (D)
Texas Instruments
16-SOIC
S-R Latch
1:1
6.8 mA
6.8 mA
Surface Mount
50 ns
18 V
3 V
Tri-State
-55 °C
125 °C
4
0.154 in
16-SOIC
3.9 mm
16-TSSOP
Texas Instruments
16-TSSOP
S-R Latch
1:1
6.8 mA
6.8 mA
Surface Mount
50 ns
18 V
3 V
Tri-State
-55 °C
125 °C
4
0.173 in
16-TSSOP
4.4 mm
16-TSSOP
Texas Instruments
16-TSSOP
S-R Latch
1:1
6.8 mA
6.8 mA
Surface Mount
50 ns
18 V
3 V
Tri-State
-55 °C
125 °C
4
0.173 in
16-TSSOP
4.4 mm
16-DIP SOT38-1
Texas Instruments
16-PDIP
S-R Latch
1:1
6.8 mA
6.8 mA
Through Hole
50 ns
18 V
3 V
Tri-State
-55 °C
125 °C
4
16-DIP
0.3 in
7.62 mm
16-TSSOP
Texas Instruments
16-TSSOP
S-R Latch
1:1
6.8 mA
6.8 mA
Surface Mount
50 ns
18 V
3 V
Tri-State
-55 °C
125 °C
4
0.173 in
16-TSSOP
4.4 mm
16-TSSOP
Texas Instruments
16-TSSOP
S-R Latch
1:1
6.8 mA
6.8 mA
Surface Mount
50 ns
18 V
3 V
Tri-State
-55 °C
125 °C
4
0.173 in
16-TSSOP
4.4 mm
PDIP (N)
Texas Instruments
16-PDIP
S-R Latch
1:1
6.8 mA
6.8 mA
Through Hole
50 ns
18 V
3 V
Tri-State
-55 °C
125 °C
4
16-DIP
0.3 in
7.62 mm

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 0.42
10$ 0.36
25$ 0.33
100$ 0.27
250$ 0.25
500$ 0.21
1000$ 0.16
Digi-Reel® 1$ 0.42
10$ 0.36
25$ 0.33
100$ 0.27
250$ 0.25
500$ 0.21
1000$ 0.16
Tape & Reel (TR) 2000$ 0.15
6000$ 0.14
10000$ 0.13
50000$ 0.12
Texas InstrumentsLARGE T&R 1$ 0.27
100$ 0.18
250$ 0.14
1000$ 0.09

Description

General part information

CD4044B Series

CD4043B types are quad cross-coupled 3-state CMOS NOR latches and the CD4044B types are quad cross-coupled 3-state CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic "1" or high on the ENABLE input connects the latch states to the Q outputs. A logic "0" or low on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The open circuit feature allows common busing of the outputs.

The CD4043B and CD4044B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline package (D, DR, DT, DWR, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4043B types are quad cross-coupled 3-state CMOS NOR latches and the CD4044B types are quad cross-coupled 3-state CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic "1" or high on the ENABLE input connects the latch states to the Q outputs. A logic "0" or low on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The open circuit feature allows common busing of the outputs.