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CD4044BE

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Texas Instruments

CMOS QUAD NAND R/S LATCH WITH 3-STATE OUTPUTS

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PDIP (N)
Integrated Circuits (ICs)

CD4044BE

Active
Texas Instruments

CMOS QUAD NAND R/S LATCH WITH 3-STATE OUTPUTS

Technical Specifications

Parameters and characteristics for this part

SpecificationCD4044BE
Circuit1:1
Current - Output High, Low [custom]6.8 mA
Current - Output High, Low [custom]6.8 mA
Delay Time - Propagation50 ns
Independent Circuits4
Logic TypeS-R Latch
Mounting TypeThrough Hole
Operating Temperature [Max]125 °C
Operating Temperature [Min]-55 °C
Output TypeTri-State
Package / Case0.3 in
Package / Case16-DIP
Package / Case7.62 mm
Supplier Device Package16-PDIP
Voltage - Supply [Max]18 V
Voltage - Supply [Min]3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1$ 0.60
10$ 0.53
25$ 0.50
100$ 0.41
250$ 0.38
500$ 0.32
1000$ 0.26
1307$ 0.23
2500$ 0.23
5000$ 0.22
Texas InstrumentsTUBE 1$ 0.46
100$ 0.31
250$ 0.24
1000$ 0.16

Description

General part information

CD4044B Series

CD4043B types are quad cross-coupled 3-state CMOS NOR latches and the CD4044B types are quad cross-coupled 3-state CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic "1" or high on the ENABLE input connects the latch states to the Q outputs. A logic "0" or low on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The open circuit feature allows common busing of the outputs.

The CD4043B and CD4044B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline package (D, DR, DT, DWR, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4043B types are quad cross-coupled 3-state CMOS NOR latches and the CD4044B types are quad cross-coupled 3-state CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic "1" or high on the ENABLE input connects the latch states to the Q outputs. A logic "0" or low on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The open circuit feature allows common busing of the outputs.