
CD4522BPW
ObsoleteCMOS PROGRAMMABLE BCD DIVIDE-BY-N COUNTER
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CD4522BPW
ObsoleteCMOS PROGRAMMABLE BCD DIVIDE-BY-N COUNTER
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Technical Specifications
Parameters and characteristics for this part
| Specification | CD4522BPW |
|---|---|
| Count Rate | 8 MHz |
| Direction | Down |
| Logic Type | Divide-by-N |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 4 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Package / Case | 16-TSSOP |
| Package / Case [x] | 0.173 in |
| Package / Case [y] | 4.4 mm |
| Reset | Asynchronous |
| Supplier Device Package | 16-TSSOP |
| Trigger Type | Negative, Positive |
| Voltage - Supply [Max] | 18 V |
| Voltage - Supply [Min] | 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tube | 1 | $ 0.60 | |
| 10 | $ 0.53 | |||
| 90 | $ 0.41 | |||
| 270 | $ 0.38 | |||
| 540 | $ 0.32 | |||
| 1080 | $ 0.26 | |||
| Texas Instruments | TUBE | 1 | $ 0.53 | |
| 100 | $ 0.36 | |||
| 250 | $ 0.28 | |||
| 1000 | $ 0.18 | |||
Description
General part information
CD4522B Series
CD4522B programmable BCD counter has a decoded "0" state output for divide-by-N applications. In single stage operation the "0" output is tied to the Preset Enable input. The Cascade Feedback allows multiple stage divide-by-N operation without the need for external gating. A HIGH on the Clock Inhibit disables the pulse-counting function. A HIGH on the Master Reset asynchronously resets the divide-by-N operation. The output is presented in BCD format.
The CD4522B-series types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
CD4522B programmable BCD counter has a decoded "0" state output for divide-by-N applications. In single stage operation the "0" output is tied to the Preset Enable input. The Cascade Feedback allows multiple stage divide-by-N operation without the need for external gating. A HIGH on the Clock Inhibit disables the pulse-counting function. A HIGH on the Master Reset asynchronously resets the divide-by-N operation. The output is presented in BCD format.
Documents
Technical documentation and resources