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16-TSSOP
Integrated Circuits (ICs)

CD4522BPW

Obsolete
Texas Instruments

CMOS PROGRAMMABLE BCD DIVIDE-BY-N COUNTER

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16-TSSOP
Integrated Circuits (ICs)

CD4522BPW

Obsolete
Texas Instruments

CMOS PROGRAMMABLE BCD DIVIDE-BY-N COUNTER

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationCD4522BPW
Count Rate8 MHz
DirectionDown
Logic TypeDivide-by-N
Mounting TypeSurface Mount
Number of Bits per Element4
Number of Elements1
Operating Temperature [Max]125 °C
Operating Temperature [Min]-55 °C
Package / Case16-TSSOP
Package / Case [x]0.173 in
Package / Case [y]4.4 mm
ResetAsynchronous
Supplier Device Package16-TSSOP
Trigger TypeNegative, Positive
Voltage - Supply [Max]18 V
Voltage - Supply [Min]3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1$ 0.60
10$ 0.53
90$ 0.41
270$ 0.38
540$ 0.32
1080$ 0.26
Texas InstrumentsTUBE 1$ 0.53
100$ 0.36
250$ 0.28
1000$ 0.18

Description

General part information

CD4522B Series

CD4522B programmable BCD counter has a decoded "0" state output for divide-by-N applications. In single stage operation the "0" output is tied to the Preset Enable input. The Cascade Feedback allows multiple stage divide-by-N operation without the need for external gating. A HIGH on the Clock Inhibit disables the pulse-counting function. A HIGH on the Master Reset asynchronously resets the divide-by-N operation. The output is presented in BCD format.

The CD4522B-series types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4522B programmable BCD counter has a decoded "0" state output for divide-by-N applications. In single stage operation the "0" output is tied to the Preset Enable input. The Cascade Feedback allows multiple stage divide-by-N operation without the need for external gating. A HIGH on the Clock Inhibit disables the pulse-counting function. A HIGH on the Master Reset asynchronously resets the divide-by-N operation. The output is presented in BCD format.

Documents

Technical documentation and resources