CD4522B Series

CMOS Programmable BCD Divide-By-N Counter

Catalog

CMOS Programmable BCD Divide-By-N Counter

Part	Operating Temperature [Min]	Operating Temperature [Max]	Supplier Device Package	Number of Bits per Element	Count Rate	Reset	Trigger Type	Number of Elements	Logic Type	Package / Case	Package / Case [x]	Package / Case [y]	Mounting Type	Direction	Voltage - Supply [Max]	Voltage - Supply [Min]	Package / Case	Package / Case
Texas Instruments CD4522BMT	-55 °C	125 °C	16-SOIC	4	8 MHz	Asynchronous	Negative Positive	1	Divide-by-N	16-SOIC	0.154 in	3.9 mm	Surface Mount	Down	18 V	3 V
Texas Instruments CD4522BM	-55 °C	125 °C	16-SOIC	4	8 MHz	Asynchronous	Negative Positive	1	Divide-by-N	16-SOIC	0.154 in	3.9 mm	Surface Mount	Down	18 V	3 V
Texas Instruments CD4522BPWE4	-55 °C	125 °C	16-TSSOP	4	8 MHz	Asynchronous	Negative Positive	1	Divide-by-N	16-TSSOP	0.173 in	4.4 mm	Surface Mount	Down	18 V	3 V
Texas Instruments CD4522BM96G4	-55 °C	125 °C	16-SOIC	4	8 MHz	Asynchronous	Negative Positive	1	Divide-by-N	16-SOIC	0.154 in	3.9 mm	Surface Mount	Down	18 V	3 V
Texas Instruments CD4522BPW	-55 °C	125 °C	16-TSSOP	4	8 MHz	Asynchronous	Negative Positive	1	Divide-by-N	16-TSSOP	0.173 in	4.4 mm	Surface Mount	Down	18 V	3 V
Texas Instruments CD4522BM96	-55 °C	125 °C	16-SOIC	4	8 MHz	Asynchronous	Negative Positive	1	Divide-by-N	16-SOIC	0.154 in	3.9 mm	Surface Mount	Down	18 V	3 V
Texas Instruments CD4522BE	-55 °C	125 °C	16-PDIP	4	8 MHz	Asynchronous	Negative Positive	1	Divide-by-N	16-DIP			Through Hole	Down	18 V	3 V	0.3 in	7.62 mm

Catalog

CMOS Programmable BCD Divide-By-N Counter

Key Features

• Internally synchronous for high internal and external speedsLogic edge-clocked design — increments on positive Clock transition or on negative Clock inhibit transition.100% tested for quiescent current at 20-V5-V, 10-V, and 15-V parametric ratingsStandard symmetrical output characteristicsMaximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°CMeets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"Applications:Frequency synthesizersPhase-locked loopsProgrammable down countersProgrammable frequency dividersNOT RECOMMENDED FOR NEW DESIGNSInternally synchronous for high internal and external speedsLogic edge-clocked design — increments on positive Clock transition or on negative Clock inhibit transition.100% tested for quiescent current at 20-V5-V, 10-V, and 15-V parametric ratingsStandard symmetrical output characteristicsMaximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°CMeets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"Applications:Frequency synthesizersPhase-locked loopsProgrammable down countersProgrammable frequency dividersNOT RECOMMENDED FOR NEW DESIGNS

Description

CD4522B programmable BCD counter has a decoded "0" state output for divide-by-N applications. In single stage operation the "0" output is tied to the Preset Enable input. The Cascade Feedback allows multiple stage divide-by-N operation without the need for external gating. A HIGH on the Clock Inhibit disables the pulse-counting function. A HIGH on the Master Reset asynchronously resets the divide-by-N operation. The output is presented in BCD format. The CD4522B-series types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). CD4522B programmable BCD counter has a decoded "0" state output for divide-by-N applications. In single stage operation the "0" output is tied to the Preset Enable input. The Cascade Feedback allows multiple stage divide-by-N operation without the need for external gating. A HIGH on the Clock Inhibit disables the pulse-counting function. A HIGH on the Master Reset asynchronously resets the divide-by-N operation. The output is presented in BCD format. The CD4522B-series types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).