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Integrated Circuits (ICs)

CD4522BM

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Texas Instruments

COUNTER/DIVIDER SINGLE 4-BIT DECADE DOWN 16-PIN SOIC TUBE

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Product Image
Integrated Circuits (ICs)

CD4522BM

Active
Texas Instruments

COUNTER/DIVIDER SINGLE 4-BIT DECADE DOWN 16-PIN SOIC TUBE

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationCD4522BM
Count Rate8 MHz
DirectionDown
Logic TypeDivide-by-N
Mounting TypeSurface Mount
Number of Bits per Element4
Number of Elements1
Operating Temperature [Max]125 °C
Operating Temperature [Min]-55 °C
Package / Case16-SOIC
Package / Case [x]0.154 in
Package / Case [y]3.9 mm
ResetAsynchronous
Supplier Device Package16-SOIC
Trigger TypeNegative, Positive
Voltage - Supply [Max]18 V
Voltage - Supply [Min]3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1$ 0.43
10$ 0.37
40$ 0.34
120$ 0.27
280$ 0.25
520$ 0.22
1000$ 0.17
LCSCPiece 1$ 0.49
200$ 0.19
500$ 0.18
1000$ 0.18
Texas InstrumentsTUBE 1$ 0.46
100$ 0.31
250$ 0.24
1000$ 0.16

Description

General part information

CD4522B Series

CD4522B programmable BCD counter has a decoded "0" state output for divide-by-N applications. In single stage operation the "0" output is tied to the Preset Enable input. The Cascade Feedback allows multiple stage divide-by-N operation without the need for external gating. A HIGH on the Clock Inhibit disables the pulse-counting function. A HIGH on the Master Reset asynchronously resets the divide-by-N operation. The output is presented in BCD format.

The CD4522B-series types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4522B programmable BCD counter has a decoded "0" state output for divide-by-N applications. In single stage operation the "0" output is tied to the Preset Enable input. The Cascade Feedback allows multiple stage divide-by-N operation without the need for external gating. A HIGH on the Clock Inhibit disables the pulse-counting function. A HIGH on the Master Reset asynchronously resets the divide-by-N operation. The output is presented in BCD format.

Documents

Technical documentation and resources