AT91SAM7S512B-AU
ActiveARM MCU, SAM7S SERIES, SAM 32 FAMILY AT91SAM7S SERIES MICROCONTROLLERS, ARM7TDMI, 32 BIT, 55 MHZ
Deep-Dive with AI
Search across all available documentation for this part.
AT91SAM7S512B-AU
ActiveARM MCU, SAM7S SERIES, SAM 32 FAMILY AT91SAM7S SERIES MICROCONTROLLERS, ARM7TDMI, 32 BIT, 55 MHZ
Technical Specifications
Parameters and characteristics for this part
| Specification | AT91SAM7S512B-AU |
|---|---|
| Connectivity | USB, SSC, UART/USART, I2C, SPI |
| Core Processor | ARM7® |
| Core Size [Max] | 32 Bit |
| Core Size [Min] | 16 Bit |
| Data Converters [custom] | 8 |
| Data Converters [custom] | 10 |
| Mounting Type | Surface Mount |
| Number of I/O | 32 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Oscillator Type | Internal |
| Package / Case | 64-LQFP |
| Peripherals | Brown-out Detect/Reset, DMA, POR, WDT, PWM |
| Program Memory Size | 512 KB |
| Program Memory Type | FLASH |
| RAM Size | 64 K |
| Speed | 55 MHz |
| Supplier Device Package | 64-LQFP (10x10) |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tray | 1 | $ 14.58 | |
| 25 | $ 13.27 | |||
| 100 | $ 12.01 | |||
| Microchip Direct | TRAY | 1 | $ 14.58 | |
| 25 | $ 13.27 | |||
| 100 | $ 12.01 | |||
| 1000 | $ 10.98 | |||
| 5000 | $ 10.53 | |||
| Newark | Each | 25 | $ 14.89 | |
Description
General part information
AT91SAM7S512 Series
Microchip's ARM®-based SAM7S512 is a member of the SAM7S series of flash microcontrollers based on the 32-bit ARM7TDMI RISC processor. It operates at a maximum speed of 55MHz and features 512KB of dual bank flash memory and 64KB of SRAM.
The peripheral set includes a Full Speed USB device and PHY at 12Mbps, UART, two USARTs, TWI (I2C), SPI, SSC, two PWM timers, three 16-bit timers,RTT, 8x10-bit ADC and 32 IO lines.
It achieves single-cycle instruction access from embedded flash at 27 MIPS. The multi-layer bus matrix, multiple SRAM banks, PDC, and DMA support parallel tasks and maximize data throughput.
Documents
Technical documentation and resources
