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32-LQFP
Integrated Circuits (ICs)

CDCLVP110MVFR

Active
Texas Instruments

1:10 LVPECL/HSTL TO LVPECL CLOCK DRIVER

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32-LQFP
Integrated Circuits (ICs)

CDCLVP110MVFR

Active
Texas Instruments

1:10 LVPECL/HSTL TO LVPECL CLOCK DRIVER

Technical Specifications

Parameters and characteristics for this part

SpecificationCDCLVP110MVFR
Differential - Input:Output [custom]True
Differential - Input:Output [custom]True
Frequency - Max [Max]3.5 GHz
InputLVPECL, HSTL
Mounting TypeSurface Mount
Number of Circuits1
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
OutputLVPECL
Package / Case32-LQFP
Ratio - Input:Output [custom]10
Ratio - Input:Output [custom]2
Supplier Device Package32-LQFP (7x7)
TypeFanout Buffer (Distribution), Multiplexer
Voltage - Supply [Max]3.8 V
Voltage - Supply [Min]2.375 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTape & Reel (TR) 1000$ 7.51
Texas InstrumentsLARGE T&R 1$ 10.29
100$ 8.38
250$ 6.59
1000$ 5.59

Description

General part information

CDCLVP110 Series

The CDCLVP110 clock driver distributes one differential clock pair of either LVPECL or HSTL (selectable) input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP110 can accept two clock sources into an input multiplexer. The CLK0 input accepts either LVECL/LVPECL input signals, while CLK1 accepts an HSTL input signal when operated under LVPECL conditions. The CDCLVP110 is specifically designed for driving 50-Ω transmission lines.

The VBB reference voltage output is used if single-ended input operation is required. In this case the VBB pin should be connected toCLK0and bypassed to GND via a 10-nF capacitor.

However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.