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Technical Specifications
Parameters and characteristics for this part
| Specification | CDCLVP110MVFRG4 |
|---|---|
| Differential - Input:Output [custom] | True |
| Differential - Input:Output [custom] | True |
| Frequency - Max [Max] | 3.5 GHz |
| Input | LVPECL, HSTL |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output | LVPECL |
| Package / Case | 32-LQFP |
| Ratio - Input:Output [custom] | 10 |
| Ratio - Input:Output [custom] | 2 |
| Supplier Device Package | 32-LQFP (7x7) |
| Type | Fanout Buffer (Distribution), Multiplexer |
| Voltage - Supply [Max] | 3.8 V |
| Voltage - Supply [Min] | 2.375 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tape & Reel (TR) | 1000 | $ 7.51 | |
Description
General part information
CDCLVP110 Series
The CDCLVP110 clock driver distributes one differential clock pair of either LVPECL or HSTL (selectable) input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP110 can accept two clock sources into an input multiplexer. The CLK0 input accepts either LVECL/LVPECL input signals, while CLK1 accepts an HSTL input signal when operated under LVPECL conditions. The CDCLVP110 is specifically designed for driving 50-Ω transmission lines.
The VBB reference voltage output is used if single-ended input operation is required. In this case the VBB pin should be connected toCLK0and bypassed to GND via a 10-nF capacitor.
However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.
Documents
Technical documentation and resources
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