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CDCLVP110

CDCLVP110 Series

1:10 LVPECL/HSTL to LVPECL clock driver

Manufacturer: Texas Instruments

Catalog

1:10 LVPECL/HSTL to LVPECL clock driver

Key Features

Distributes One Differential Clock Input PairLVPECL/HSTL to 10 Differential LVPECL Clock OutputsFully Compatible With LVECL/LVPECL/HSTLSingle Supply Voltage Required, ±3.3-V or ±2.5-V SupplySelectable Clock Input Through CLK_SELLow-Output Skew (Typ 15 ps) for Clock-Distribution ApplicationsVBB Reference Voltage Output for Single-Ended ClockingAvailable in a 32-Pin LQFP PackageFrequency Range From DC to 3.5 GHzPin-to-Pin Compatible With MC100 Series EP111, ES6111, LVEP111, PTN1111Distributes One Differential Clock Input PairLVPECL/HSTL to 10 Differential LVPECL Clock OutputsFully Compatible With LVECL/LVPECL/HSTLSingle Supply Voltage Required, ±3.3-V or ±2.5-V SupplySelectable Clock Input Through CLK_SELLow-Output Skew (Typ 15 ps) for Clock-Distribution ApplicationsVBB Reference Voltage Output for Single-Ended ClockingAvailable in a 32-Pin LQFP PackageFrequency Range From DC to 3.5 GHzPin-to-Pin Compatible With MC100 Series EP111, ES6111, LVEP111, PTN1111

Description

AI
The CDCLVP110 clock driver distributes one differential clock pair of either LVPECL or HSTL (selectable) input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP110 can accept two clock sources into an input multiplexer. The CLK0 input accepts either LVECL/LVPECL input signals, while CLK1 accepts an HSTL input signal when operated under LVPECL conditions. The CDCLVP110 is specifically designed for driving 50-Ω transmission lines. The VBB reference voltage output is used if single-ended input operation is required. In this case the VBB pin should be connected toCLK0and bypassed to GND via a 10-nF capacitor. However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended. The CDCLVP110 is characterized for operation from –40°C to 85°C. The CDCLVP110 clock driver distributes one differential clock pair of either LVPECL or HSTL (selectable) input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP110 can accept two clock sources into an input multiplexer. The CLK0 input accepts either LVECL/LVPECL input signals, while CLK1 accepts an HSTL input signal when operated under LVPECL conditions. The CDCLVP110 is specifically designed for driving 50-Ω transmission lines. The VBB reference voltage output is used if single-ended input operation is required. In this case the VBB pin should be connected toCLK0and bypassed to GND via a 10-nF capacitor. However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended. The CDCLVP110 is characterized for operation from –40°C to 85°C.