CDCLVP1102RGTT
ActiveLOW JITTER 1:2 UNIVERSAL-TO-LVPECL BUFFER
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CDCLVP1102RGTT
ActiveLOW JITTER 1:2 UNIVERSAL-TO-LVPECL BUFFER
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | CDCLVP1102RGTT |
|---|---|
| Differential - Input:Output [custom] | True |
| Differential - Input:Output [custom] | True |
| Frequency - Max [Max] | 2 GHz |
| Input | LVCMOS, LVTTL, LVPECL, LVDS |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output | LVPECL |
| Package / Case | 16-VFQFN Exposed Pad |
| Ratio - Input:Output [custom] | 1:2 |
| Supplier Device Package | 16-VQFN (3x3) |
| Type | Fanout Buffer (Distribution) |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 2.375 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 8.47 | |
| 10 | $ 5.83 | |||
| 25 | $ 5.15 | |||
| 100 | $ 4.38 | |||
| Digi-Reel® | 1 | $ 8.47 | ||
| 10 | $ 5.83 | |||
| 25 | $ 5.15 | |||
| 100 | $ 4.38 | |||
| Tape & Reel (TR) | 250 | $ 4.01 | ||
| 500 | $ 3.78 | |||
| 750 | $ 3.67 | |||
| 1250 | $ 3.54 | |||
| 1750 | $ 3.47 | |||
| 2500 | $ 3.46 | |||
| Texas Instruments | SMALL T&R | 1 | $ 5.10 | |
| 100 | $ 4.16 | |||
| 250 | $ 3.27 | |||
| 1000 | $ 2.77 | |||
Description
General part information
CDCLVP1102 Series
The CDCLVP1102 is a highly versatile, low additive jitter buffer that can generate two copies of LVPECL clock outputs from one LVPECL, LVDS, or LVCMOS input for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 10 ps, making the device a perfect choice for use in demanding applications.
The CDCLVP1102 clock buffer distributes a single clock input (IN) to two pairs of differential LVPECL clock outputs (OUT0, OUT1) with minimum skew for clock distribution. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.
The CDCLVP1102 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.
Documents
Technical documentation and resources
