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SN74LS374N

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Texas Instruments

FLIP FLOP D-TYPE BUS INTERFACE POS-EDGE 3-ST 1-ELEMENT 20-PIN PDIP TUBE

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PDIP (N)
Integrated Circuits (ICs)

SN74LS374N

Active
Texas Instruments

FLIP FLOP D-TYPE BUS INTERFACE POS-EDGE 3-ST 1-ELEMENT 20-PIN PDIP TUBE

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74LS374N
Clock Frequency50 MHz
Current - Output High, Low [custom]24 mA
Current - Output High, Low [custom]2.6 mA
Current - Quiescent (Iq)40 mA
FunctionStandard
Max Propagation Delay @ V, Max CL28 ns
Mounting TypeThrough Hole
Number of Bits per Element8
Number of Elements1
Operating Temperature [Max]70 °C
Operating Temperature [Min]0 °C
Output TypeTri-State, Non-Inverted
Package / Case20-DIP
Package / Case7.62 mm
Package / Case0.3 in
Supplier Device Package20-PDIP
Trigger TypePositive Edge
TypeD-Type
Voltage - Supply [Max]5.25 V
Voltage - Supply [Min]4.75 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
ArrowN/A 1$ 0.71
10$ 0.64
20$ 0.56
100$ 0.52
260$ 0.50
500$ 0.48
DigikeyTube 1$ 1.24
20$ 1.11
40$ 1.05
100$ 0.86
260$ 0.81
500$ 0.71
1000$ 0.56
2500$ 0.53
5000$ 0.50
Texas InstrumentsTUBE 1$ 0.92
100$ 0.71
250$ 0.52
1000$ 0.37

Description

General part information

SN74LS374 Series

These 8-bit registers feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance 3-state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pullup components. These devices are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight latches of the ’LS373 and ’S373 are transparent D-type latches, meaning that while the enable (C or CLK) input is high, the Q outputs follow the data (D) inputs. When C or CLK is taken low, the output is latched at the level of the data that was set up.

The eight flip-flops of the ’LS374 and ’S374 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic states that were set up at the D inputs.