Specification	SY69753ALHG-TR

Differential - Input:Output [custom]	True
Differential - Input:Output [custom]	True
Frequency - Max [Max]	155 Mbps
Input	PECL
Main Purpose	Ethernet, SONET/SDH, ATM OC-3
Mounting Type	Surface Mount
Number of Circuits	1
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output	PECL
Package / Case	32-TQFP Exposed Pad
PLL	True
Ratio - Input:Output [custom]	1:3
Supplier Device Package	32-TQFP-EP
Supplier Device Package [custom]	7x7
Voltage - Supply [Max]	3.45 V
Voltage - Supply [Min]	3.15 V

SY69753AL Series

Part	Package / Case	Main Purpose	Voltage - Supply [Max]	Voltage - Supply [Min]	Mounting Type	Ratio - Input:Output [custom]	Output	Frequency - Max [Max]	Number of Circuits	Supplier Device Package [custom]	Supplier Device Package	Operating Temperature [Max]	Operating Temperature [Min]	Input
Microchip Technology SY69753ALHG-TR	32-TQFP Exposed Pad	ATM OC-3 Ethernet SONET/SDH	3.45 V	3.15 V	Surface Mount	1:3	PECL	155 Mbps	1	7x7	32-TQFP-EP	85 °C	-40 °C	PECL
Microchip Technology SY69753LHI-TR	32-TQFP Exposed Pad	ATM OC-3 Ethernet SONET/SDH	3.45 V	3.15 V	Surface Mount	1:3	PECL	155 Mbps	1	7x7	32-TQFP-EP	85 °C	-40 °C	PECL
Microchip Technology SY69753LHC	32-TQFP Exposed Pad	ATM OC-3 Ethernet SONET/SDH	3.45 V	3.15 V	Surface Mount	1:3	PECL	155 Mbps	1	7x7	32-TQFP-EP	85 °C	-40 °C	PECL
Microchip Technology SY69753LHI	32-TQFP Exposed Pad	ATM OC-3 Ethernet SONET/SDH	3.45 V	3.15 V	Surface Mount	1:3	PECL	155 Mbps	1	7x7	32-TQFP-EP	85 °C	-40 °C	PECL
Microchip Technology SY69753ALHG	32-TQFP Exposed Pad	ATM OC-3 Ethernet SONET/SDH	3.45 V	3.15 V	Surface Mount	1:3	PECL	155 Mbps	1	7x7	32-TQFP-EP	85 °C	-40 °C	PECL

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tape & Reel (TR)	1000	$ 14.96
Microchip Direct	T/R	1	$ 19.75
		25	$ 16.46
		100	$ 14.96
		1000	$ 13.82
		5000	$ 13.11

Description

General part information

SY69753AL Series

The SY69753AL is a complete Clock Recovery and Data Retiming integrated circuit for OC-3/STS-3 applications at 155Mbps NRZ. The device is ideally suited for SONET/SDH/ATM applications and other high-speed data transmission systems.

Clock recovery and data retiming is performed by synchronizing the on-chip VCO directly to the incoming data stream. The VCO center frequency is controlled by the reference clock frequency and the selected divide ratio. On-chip clock generation is performed through the use of a frequency multiplier PLL with a byte rate source as reference.

The SY69753AL also includes a link fault detection circuit.

Documents

Technical documentation and resources

SY69753AL/754AL Evaluation Board User's Guide

User Guide

SY69753AL Data Sheet

Data Sheets