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TSSOP (PW)
Integrated Circuits (ICs)

DAC8812ICPW

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Texas Instruments

16-BIT, DUAL SERIAL INPUT MULTIPLYING DIGITAL-TO-ANALOG CONVERTER

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TSSOP (PW)
Integrated Circuits (ICs)

DAC8812ICPW

Active
Texas Instruments

16-BIT, DUAL SERIAL INPUT MULTIPLYING DIGITAL-TO-ANALOG CONVERTER

Technical Specifications

Parameters and characteristics for this part

SpecificationDAC8812ICPW
ArchitectureMultiplying DAC
Data InterfaceSPI
Differential OutputFalse
INL/DNL (LSB)±1 (Max)
Mounting TypeSurface Mount
Number of Bits16
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Output TypeCurrent - Unbuffered
Package / Case16-TSSOP
Package / Case [x]0.173 in
Package / Case [y]4.4 mm
Reference TypeExternal
Settling Time500 ns
Supplier Device Package16-TSSOP
Voltage - Supply, Analog [Max]5.5 V
Voltage - Supply, Analog [Min]2.7 V
Voltage - Supply, Digital [Max]5.5 V
Voltage - Supply, Digital [Min]2.7 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1$ 28.70
10$ 26.47
90$ 22.61
270$ 21.56
Texas InstrumentsTUBE 1$ 24.44
100$ 21.35
250$ 16.46
1000$ 14.72

Description

General part information

DAC8812 Series

The DAC8812 is a dual, 16-bit, current-output digital-to-analog converter (DAC) designed to operate from a single 2.7-V to 5.5-V supply.

The applied external reference input voltage VREFdetermines the full-scale output current. An internal feedback resistor (RFB) provides temperature tracking for the full-scale output when combined with an external I-to-V precision amplifier.

A double-buffered, serial data interface offers high-speed, 3-wire, SPI and microcontroller compatible inputs using serial data in (SDI), clock (CLK), and a chip-select (CS). A common level-sensitive load DAC strobe (LDAC) input allows simultaneous update of all DAC outputs from previously loaded input registers. Additionally, an internal power-on reset forces the output voltage to zero at system turnon. An MSB pin allows system reset assertion (RS) to force all registers to zero code when MSB = 0, or to midscale code when MSB = 1.