SN74F574DW
ObsoleteFLIP FLOP D-TYPE BUS INTERFACE POS-EDGE 3-ST 1-ELEMENT 20-PIN SOIC TUBE
Deep-Dive with AI
Search across all available documentation for this part.
SN74F574DW
ObsoleteFLIP FLOP D-TYPE BUS INTERFACE POS-EDGE 3-ST 1-ELEMENT 20-PIN SOIC TUBE
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74F574DW |
|---|---|
| Clock Frequency | 100 MHz |
| Current - Output High, Low [custom] | 3 mA |
| Current - Output High, Low [custom] | 24 mA |
| Function | Standard |
| Max Propagation Delay @ V, Max CL | 8.5 ns |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 8 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 70 °C |
| Operating Temperature [Min] | 0 °C |
| Output Type | Tri-State, Non-Inverted |
| Package / Case | 20-SOIC |
| Package / Case [y] | 0.295 in |
| Package / Case [y] | 7.5 mm |
| Supplier Device Package | 20-SOIC |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 4.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tube | 1 | $ 1.06 | |
| 10 | $ 0.94 | |||
| 25 | $ 0.90 | |||
| 100 | $ 0.74 | |||
| 250 | $ 0.69 | |||
| 500 | $ 0.61 | |||
| Texas Instruments | TUBE | 1 | $ 0.78 | |
| 100 | $ 0.60 | |||
| 250 | $ 0.44 | |||
| 1000 | $ 0.32 | |||
Description
General part information
SN74F574 Series
This 8-bit flip-flop features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight flip-flops of the SN74F574 are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs will be set to the logic levels that were set up at the data (D) inputs.
A buffered output enableinput can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.
Documents
Technical documentation and resources
