Specification	SN74ABT374ANSR

Clock Frequency	200 MHz
Current - Output High, Low [custom]	64 mA
Current - Output High, Low [custom]	32 mA
Function	Standard
Input Capacitance	3.5 pF
Max Propagation Delay @ V, Max CL	6.6 ns
Mounting Type	Surface Mount
Number of Bits per Element	8
Number of Elements	1
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output Type	Tri-State, Non-Inverted
Package / Case	20-SOIC
Package / Case	0.209 "
Package / Case	5.3 mm
Supplier Device Package	20-SO
Trigger Type	Positive Edge
Type	D-Type
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	4.5 V

SN74ABT374A Series

Octal Edge-Triggered D-Type Flip-Flops with 3-State Outputs

Part	Input Capacitance	Number of Bits per Element	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Trigger Type	Supplier Device Package	Output Type	Max Propagation Delay @ V, Max CL	Operating Temperature [Max]	Operating Temperature [Min]	Package / Case	Mounting Type	Number of Elements	Voltage - Supply [Min]	Voltage - Supply [Max]	Function	Clock Frequency	Type	Package / Case [y]	Package / Case [x]	Package / Case [y]	Package / Case	Package / Case
Texas Instruments SN74ABT374ADBR	3.5 pF	8	64 mA	32 mA	Positive Edge	20-SSOP	Non-Inverted Tri-State	6.6 ns	85 °C	-40 °C	20-SSOP	Surface Mount	1	4.5 V	5.5 V	Standard	200 MHz	D-Type
Texas Instruments SN74ABT374N
Texas Instruments SN74ABT374APW	3.5 pF	8	64 mA	32 mA	Positive Edge	20-TSSOP	Non-Inverted Tri-State	6.6 ns	85 °C	-40 °C	20-TSSOP	Surface Mount	1	4.5 V	5.5 V	Standard	200 MHz	D-Type	4.4 mm	0.173 in
Texas Instruments SN74ABT374ADW	3.5 pF	8	64 mA	32 mA	Positive Edge	20-SOIC	Non-Inverted Tri-State	5.1 ns	85 °C	-40 °C	20-SOIC	Surface Mount	1	4.5 V	5.5 V	Standard	200 MHz	D-Type	0.295 in		7.5 mm
Texas Instruments SN74ABT374APWR	3.5 pF	8	64 mA	32 mA	Positive Edge	20-TSSOP	Non-Inverted Tri-State	6.6 ns	85 °C	-40 °C	20-TSSOP	Surface Mount	1	4.5 V	5.5 V	Standard	200 MHz	D-Type	4.4 mm	0.173 in
Texas Instruments SN74ABT374DBLE
Texas Instruments SN74ABT374ADWRG4	3.5 pF	8	64 mA	32 mA	Positive Edge	20-SOIC	Non-Inverted Tri-State	6.6 ns	85 °C	-40 °C	20-SOIC	Surface Mount	1	4.5 V	5.5 V	Standard	200 MHz	D-Type	0.295 in		7.5 mm
Texas Instruments SN74ABT374ANSR	3.5 pF	8	64 mA	32 mA	Positive Edge	20-SO	Non-Inverted Tri-State	6.6 ns	85 °C	-40 °C	20-SOIC	Surface Mount	1	4.5 V	5.5 V	Standard	200 MHz	D-Type				0.209 "	5.3 mm

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Cut Tape (CT)	1	$ 1.21
	Digi-Reel®	1	$ 1.21
	Tape & Reel (TR)	2000	$ 0.51
		6000	$ 0.49
		10000	$ 0.47
Texas Instruments	LARGE T&R	1	$ 0.90
		100	$ 0.69
		250	$ 0.51
		1000	$ 0.36

Description

General part information

SN74ABT374A Series

These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight flip-flops of the SN54ABT374 and SN74ABT374A are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.

A buffered output-enable () input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

Documents

Technical documentation and resources

SN74ABT374ANSR

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SN74ABT374ANSR

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Technical Specifications

SN74ABT374A Series

Pricing

Description

SN74ABT374A Series

Documents

Designing With Logic (Rev. C)

Selecting the Right Level Translation Solution (Rev. A)

Understanding Advanced Bus-Interface Products Design Guide

LOGIC Pocket Data Book (Rev. B)

Power-Up Behavior of Clocked Devices (Rev. B)

Implications of Slow or Floating CMOS Inputs (Rev. E)

Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs datasheet (Rev. G)

Input and Output Characteristics of Digital Integrated Circuits

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Live Insertion

Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A)

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Advanced Bus Interface Logic Selection Guide

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Quad Flatpack No-Lead Logic Packages (Rev. D)

Logic Guide (Rev. AB)

Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A)

TI IBIS File Creation, Validation, and Distribution Processes

Advanced BiCMOS Technology (ABT) Logic Characterization Information (Rev. B)

Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices

SN74ABT374A Series