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Technical Specifications
Parameters and characteristics for this part
| Specification | SY100EL32VZC |
|---|---|
| Count Rate | 3 GHz |
| Logic Type | Divide-by-2 |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 1 bits |
| Number of Elements | 1 |
| Operating Temperature (Max) | 85 °C |
| Operating Temperature (Min) | -40 °C |
| Package Length | 0.154 in |
| Package Name | 8-SOIC |
| Package Width | 3.9 mm |
| Reset | Asynchronous |
| Trigger Type | Positive, Negative |
| Voltage - Supply (Maximum) | 5 V |
| Voltage - Supply (Minimum) | 3.3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | Updated |
|---|---|---|---|---|
| Digikey | Tube | 380 | $ 1.91 | <2d |
CAD
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Description
General part information
100EL32 Series
The SY100EL32V is an integrated divide by 2 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC-coupled interface to the device. If used, the VBB output should be bypassed to ground with a 0.01 µF capacitor. Also note that the VBB is designed to be used as an input bias on the EL32V only; the VBB output has limited current sink and source capability. The Reset pin is asynchronous and is asserted on the rising edge. Upon power-on, the internal flip-flop will attain a random state. The Reset allows for the synchronization of multiple EL32Vs in a system.
Documents
Technical documentation and resources
