Specification	SN74ALS174D

Clock Frequency	50 MHz
Current - Output High, Low [custom]	400 µA
Current - Output High, Low [custom]	8 mA
Current - Quiescent (Iq)	19 mA
Max Propagation Delay @ V, Max CL	17 ns
Mounting Type	Surface Mount
Number of Bits per Element	6
Number of Elements	1
Operating Temperature [Max]	70 °C
Operating Temperature [Min]	0 °C
Output Type	Non-Inverted
Package / Case	16-SOIC
Package / Case [x]	0.154 in
Package / Case [y]	3.9 mm
Supplier Device Package	16-SOIC
Trigger Type	Positive Edge
Type	D-Type
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	4.5 V

SN74ALS174 Series

Hex D-Type Positive-Edge-Triggered Flip-Flops With Clear

Part	Max Propagation Delay @ V, Max CL	Clock Frequency	Mounting Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Supplier Device Package	Package / Case	Package / Case	Package / Case	Number of Bits per Element	Operating Temperature [Max]	Operating Temperature [Min]	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Current - Quiescent (Iq)	Type	Output Type	Trigger Type	Number of Elements	Package / Case [x]	Package / Case [y]
Texas Instruments SN74ALS174NSR	17 ns	50 MHz	Surface Mount	4.5 V	5.5 V	16-SO	0.209 "	16-SOIC	5.3 mm	6	70 °C	0 °C	400 µA	8 mA	19 mA	D-Type	Non-Inverted	Positive Edge	1
Texas Instruments SN74ALS174DR	17 ns	50 MHz	Surface Mount	4.5 V	5.5 V	16-SOIC		16-SOIC		6	70 °C	0 °C	400 µA	8 mA	19 mA	D-Type	Non-Inverted	Positive Edge	1	0.154 in	3.9 mm
Texas Instruments SN74ALS174D	17 ns	50 MHz	Surface Mount	4.5 V	5.5 V	16-SOIC		16-SOIC		6	70 °C	0 °C	400 µA	8 mA	19 mA	D-Type	Non-Inverted	Positive Edge	1	0.154 in	3.9 mm
Texas Instruments SN74ALS174FN

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tube	1	$ 1.28
		10	$ 1.15
		40	$ 1.09
		120	$ 0.89
		280	$ 0.84
		520	$ 0.74
		1000	$ 0.58
Texas Instruments	TUBE	1	$ 0.95
		100	$ 0.73
		250	$ 0.54
		1000	$ 0.39

Description

General part information

SN74ALS174 Series

These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.

Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.

These circuits are fully compatible for use with most TTL circuits.

Documents

Technical documentation and resources

Hex/Quadruple D-Type Flip-Flops With Clear datasheet (Rev. E)

Data sheet