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Texas Instruments-SN74HC4040DE4 Counter Shift Registers Counter Single 12-Bit Binary UP 16-Pin SOIC Tube
Integrated Circuits (ICs)

SN74ALS174DR

Active
Texas Instruments

FLIP FLOP D-TYPE BUS INTERFACE POS-EDGE 1-ELEMENT 16-PIN SOIC T/R

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Texas Instruments-SN74HC4040DE4 Counter Shift Registers Counter Single 12-Bit Binary UP 16-Pin SOIC Tube
Integrated Circuits (ICs)

SN74ALS174DR

Active
Texas Instruments

FLIP FLOP D-TYPE BUS INTERFACE POS-EDGE 1-ELEMENT 16-PIN SOIC T/R

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74ALS174DR
Clock Frequency50 MHz
Current - Output High, Low [custom]400 µA
Current - Output High, Low [custom]8 mA
Current - Quiescent (Iq)19 mA
Max Propagation Delay @ V, Max CL17 ns
Mounting TypeSurface Mount
Number of Bits per Element6
Number of Elements1
Operating Temperature [Max]70 °C
Operating Temperature [Min]0 °C
Output TypeNon-Inverted
Package / Case16-SOIC
Package / Case [x]0.154 in
Package / Case [y]3.9 mm
Supplier Device Package16-SOIC
Trigger TypePositive Edge
TypeD-Type
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]4.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 0.95
10$ 0.85
25$ 0.81
100$ 0.66
250$ 0.62
500$ 0.55
1000$ 0.43
Digi-Reel® 1$ 0.95
10$ 0.85
25$ 0.81
100$ 0.66
250$ 0.62
500$ 0.55
1000$ 0.43
Tape & Reel (TR) 2500$ 0.36
Texas InstrumentsLARGE T&R 1$ 0.81
100$ 0.62
250$ 0.46
1000$ 0.33

Description

General part information

SN74ALS174 Series

These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.

Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.

These circuits are fully compatible for use with most TTL circuits.