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60-WQFN
Integrated Circuits (ICs)

DS90UB926QSQ/NOPB

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Texas Instruments

5-85 MHZ 24-BIT COLOR FPD-LINK III DESERIALIZER WITH BIDIRECTIONAL CONTROL CHANNEL

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60-WQFN
Integrated Circuits (ICs)

DS90UB926QSQ/NOPB

Active
Texas Instruments

5-85 MHZ 24-BIT COLOR FPD-LINK III DESERIALIZER WITH BIDIRECTIONAL CONTROL CHANNEL

Technical Specifications

Parameters and characteristics for this part

SpecificationDS90UB926QSQ/NOPB
Data Rate2.975 Gbps
FunctionDeserializer
GradeAutomotive
Input TypeFPD-Link III, LVDS
Mounting TypeSurface Mount
Number of Inputs1
Number of Outputs24
Operating Temperature [Max]105 °C
Operating Temperature [Min]-40 °C
Output TypeLVCMOS
Package / Case60-WFQFN Exposed Pad
QualificationAEC-Q100
Supplier Device Package60-WQFN (9x9)
Voltage - Supply [Max]3.6 V, 1.89 V
Voltage - Supply [Min]3 V, 1.71 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 13.14
10$ 12.07
25$ 11.57
100$ 10.20
250$ 9.70
500$ 9.07
Digi-Reel® 1$ 13.14
10$ 12.07
25$ 11.57
100$ 10.20
250$ 9.70
500$ 9.07
Tape & Reel (TR) 1000$ 8.32
Texas InstrumentsSMALL T&R 1$ 10.28
100$ 8.98
250$ 6.92
1000$ 6.19

Description

General part information

DS90UB926Q-Q1 Series

The DS90UB926Q-Q1 deserializer, in conjunction with the DS90UB925Q-Q1 serializer, provides a complete digital interface for concurrent transmission of high-speed video, audio, and control data for automotive display and image-sensing applications.

This chipset translates a parallel RGB video interface into a single-pair high-speed serialized interface. The serial bus scheme, FPD-Link III, supports full duplex of high-speed forward data transmission and low-speed backchannel communication over a single differential link. Consolidation of video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.

The DS90UB926Q-Q1 deserializer recovers the RGB data, three video control signals, and four synchronized I2S audio signals. The device extracts the clock from a high-speed serial stream. An output LOCK pin provides the link status if the incoming data stream is locked, without the use of a training sequence or special SYNC patterns, as well as a reference clock.