
CD74HC74M
ObsoleteHIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH SET AND RESET
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CD74HC74M
ObsoleteHIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH SET AND RESET
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Technical Specifications
Parameters and characteristics for this part
| Specification | CD74HC74M |
|---|---|
| Clock Frequency | 50 MHz |
| Current - Output High, Low [custom] | 5.2 mA |
| Current - Output High, Low [custom] | 5.2 mA |
| Current - Quiescent (Iq) | 4 çA |
| Function | Reset, Set(Preset) |
| Input Capacitance | 10 pF |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 1 |
| Number of Elements | 2 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Output Type | Complementary |
| Package / Case | 14-SOIC |
| Package / Case [x] | 0.154 in |
| Package / Case [y] | 3.9 mm |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 6 V |
| Voltage - Supply [Min] | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Texas Instruments | TUBE | 1 | $ 0.77 | |
| 100 | $ 0.59 | |||
| 250 | $ 0.43 | |||
| 1000 | $ 0.31 | |||
Description
General part information
SN74HC74-EP Series
The SN74HC74 device contains two independent D-type positive edge triggered flip flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold time interval, data at the D input can be changed without affecting the levels at the outputs.
The SN74HC74 device contains two independent D-type positive edge triggered flip flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold time interval, data at the D input can be changed without affecting the levels at the outputs.
Documents
Technical documentation and resources