Specification	SN74HC74N

Clock Frequency	60 MHz
Current - Output High, Low [custom]	5.2 mA
Current - Output High, Low [custom]	5.2 mA
Current - Quiescent (Iq)	4 çA
Function	Reset, Set(Preset)
Input Capacitance	3 pF
Mounting Type	Through Hole
Number of Bits per Element	1
Number of Elements	2
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output Type	Complementary
Package / Case	14-DIP
Package / Case [x]	0.3 "
Package / Case [y]	7.62 mm
Trigger Type	Positive Edge
Type	D-Type
Voltage - Supply [Max]	6 V
Voltage - Supply [Min]	2 V

SN74HC74-EP Series

High Speed CMOS Logic Dual Positive-Edge-Triggered D-Type Flip-Flops with Set and Reset

Part	Supplier Device Package	Type	Output Type	Trigger Type	Function	Mounting Type	Clock Frequency	Current - Quiescent (Iq)	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Voltage - Supply [Min]	Voltage - Supply [Max]	Package / Case	Package / Case	Package / Case	Max Propagation Delay @ V, Max CL	Operating Temperature [Max]	Operating Temperature [Min]	Number of Bits per Element	Input Capacitance	Number of Elements	Package / Case [custom]	Package / Case [custom]	Package / Case [y]	Package / Case [x]	Operating Temperature [Max]	Operating Temperature [Min]
Texas Instruments SN74HC74ADBR	14-SSOP	D-Type	Complementary	Positive Edge	Reset Set(Preset)	Surface Mount	85 MHz	4 çA	5.2 mA	5.2 mA	2 V	6 V	5.3 mm	14-SSOP	0.209 "	26 ns	85 °C	-40 °C	1	3 pF	2
Texas Instruments SN74HC74PWT	14-TSSOP	D-Type	Complementary	Positive Edge	Reset Set(Preset)	Surface Mount	60 MHz	4 çA	5.2 mA	5.2 mA	2 V	6 V		14-TSSOP			85 °C	-40 °C	1	3 pF	2	0.173 "	4.4 mm
Texas Instruments CD74HC74E		D-Type	Complementary	Positive Edge	Reset Set(Preset)	Through Hole	50 MHz	4 çA	5.2 mA	5.2 mA	2 V	6 V		14-DIP					1	10 pF	2			7.62 mm	0.3 "	125 °C	-55 °C
Texas Instruments SN74HC74DRE4		D-Type	Complementary	Positive Edge	Reset Set(Preset)	Surface Mount	60 MHz	4 çA	5.2 mA	5.2 mA	2 V	6 V		14-SOIC			85 °C	-40 °C	1	3 pF	2			3.9 mm	0.154 in
Texas Instruments SN74HC74DBRG4	14-SSOP	D-Type	Complementary	Positive Edge	Reset Set(Preset)	Surface Mount	60 MHz	4 çA	5.2 mA	5.2 mA	2 V	6 V	5.3 mm	14-SSOP	0.209 "		85 °C	-40 °C	1	3 pF	2
Texas Instruments SN74HC74N		D-Type	Complementary	Positive Edge	Reset Set(Preset)	Through Hole	60 MHz	4 çA	5.2 mA	5.2 mA	2 V	6 V		14-DIP			85 °C	-40 °C	1	3 pF	2			7.62 mm	0.3 "
Texas Instruments CD74HC74M96		D-Type	Complementary	Positive Edge	Reset Set(Preset)	Surface Mount	50 MHz	4 çA	5.2 mA	5.2 mA	2 V	6 V		14-SOIC					1	10 pF	2			3.9 mm	0.154 in	125 °C	-55 °C
Texas Instruments SN74HC74QDRQ1		D-Type	Complementary	Positive Edge	Reset Set(Preset)	Surface Mount	60 MHz	4 çA	5.2 mA	5.2 mA	2 V	6 V		14-SOIC			125 °C	-40 °C	1	3 pF	2			3.9 mm	0.154 in
Texas Instruments CD74HC74M		D-Type	Complementary	Positive Edge	Reset Set(Preset)	Surface Mount	50 MHz	4 çA	5.2 mA	5.2 mA	2 V	6 V		14-SOIC					1	10 pF	2			3.9 mm	0.154 in	125 °C	-55 °C
Texas Instruments SN74HC74DE4		D-Type	Complementary	Positive Edge	Reset Set(Preset)	Surface Mount	60 MHz	4 çA	5.2 mA	5.2 mA	2 V	6 V		14-SOIC			85 °C	-40 °C	1	3 pF	2			3.9 mm	0.154 in

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tube	1	$ 1.58
		10	$ 1.00
		25	$ 0.85
		100	$ 0.67
		250	$ 0.59
		500	$ 0.54
		1000	$ 0.49
		2500	$ 0.45
		5000	$ 0.42
Texas Instruments	TUBE	1	$ 0.83
		100	$ 0.56
		250	$ 0.43
		1000	$ 0.29

Description

General part information

SN74HC74-EP Series

The SN74HC74 device contains two independent D-type positive edge triggered flip flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold time interval, data at the D input can be changed without affecting the levels at the outputs.

Documents

Technical documentation and resources

SNx4HC74 Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset datasheet (Rev. F)

Data sheet

Implications of Slow or Floating CMOS Inputs (Rev. E)

Application note

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Application note

Live Insertion

Application note

SN74HC74N

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SN74HC74N

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Technical Specifications

SN74HC74-EP Series

Pricing

Description

SN74HC74-EP Series

Documents

Signal Switch Data Book (Rev. A)

Logic Guide (Rev. AB)

CMOS Power Consumption and CPD Calculation (Rev. B)

Power-Up Behavior of Clocked Devices (Rev. B)

Designing With Logic (Rev. C)

Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc

SN54/74HCT CMOS Logic Family Applications and Restrictions

TI IBIS File Creation, Validation, and Distribution Processes

LOGIC Pocket Data Book (Rev. B)

Input and Output Characteristics of Digital Integrated Circuits

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

SNx4HC74 Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset datasheet (Rev. F)

Implications of Slow or Floating CMOS Inputs (Rev. E)

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Live Insertion

SN74HC74-EP Series