Integrated Circuits (ICs)

SN74LVC1G175DBVR

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FLIP FLOP D-TYPE POS-EDGE 1-ELEMENT 6-PIN SOT-23 T/R

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Search across all available documentation for this part.

DocumentsCMOS Power Consumption and CPD Calculation (Rev. B)Input and Output Characteristics of Digital Integrated Circuits +28

Integrated Circuits (ICs)

SN74LVC1G175DBVR

Active

Texas Instruments

FLIP FLOP D-TYPE POS-EDGE 1-ELEMENT 6-PIN SOT-23 T/R

Deep-Dive with AI

DocumentsCMOS Power Consumption and CPD Calculation (Rev. B)Input and Output Characteristics of Digital Integrated Circuits +28

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	SN74LVC1G175DBVR

Current - Output High, Low [x]	32 mA
Current - Output High, Low [y]	32 mA
Current - Quiescent (Iq)	10 µA
Function	Reset
Input Capacitance	3 pF
Max Propagation Delay @ V, Max CL	5 ns
Mounting Type	Surface Mount
Number of Bits per Element	1
Number of Elements	1
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-40 °C
Output Type	Non-Inverted
Package / Case	SOT-23-6
Supplier Device Package	SOT-23-6
Trigger Type	Positive Edge
Type	D-Type
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	1.65 V

SN74LVC1G175 Series

Single D-Type Flip-Flop with Asynchronous Clear

Part	Max Propagation Delay @ V, Max CL	Operating Temperature [Min]	Operating Temperature [Max]	Output Type	Current - Quiescent (Iq)	Supplier Device Package	Voltage - Supply [Max]	Voltage - Supply [Min]	Input Capacitance	Current - Output High, Low [y]	Current - Output High, Low [x]	Number of Elements	Mounting Type	Trigger Type	Function	Number of Bits per Element	Type	Package / Case
Texas Instruments 74LVC1G175DCKRG4	4 ns	-40 °C	125 °C	Non-Inverted	10 µA	SC-70-6	5.5 V	1.65 V	3 pF	32 mA	32 mA	1	Surface Mount	Positive Edge	Reset	1	D-Type	6-TSSOP SC-88 SOT-363
Texas Instruments SN74LVC1G175DRYR	5 ns	-40 °C	125 °C	Non-Inverted	10 µA	6-SON (1.45x1)	5.5 V	1.65 V	3 pF	32 mA	32 mA	1	Surface Mount	Positive Edge	Reset	1	D-Type	6-UFDFN
Texas Instruments SN74LVC1G175DBVR	5 ns	-40 °C	125 °C	Non-Inverted	10 µA	SOT-23-6	5.5 V	1.65 V	3 pF	32 mA	32 mA	1	Surface Mount	Positive Edge	Reset	1	D-Type	SOT-23-6
Texas Instruments SN74LVC1G175DCKT	5 ns	-40 °C	125 °C	Non-Inverted	10 µA	SC-70-6	5.5 V	1.65 V	3 pF	32 mA	32 mA	1	Surface Mount	Positive Edge	Reset	1	D-Type	6-TSSOP SC-88 SOT-363
Texas Instruments SN74LVC1G175DCKR	5 ns	-40 °C	125 °C	Non-Inverted	10 µA	SC-70-6	5.5 V	1.65 V	3 pF	32 mA	32 mA	1	Surface Mount	Positive Edge	Reset	1	D-Type	6-TSSOP SC-88 SOT-363

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Cut Tape (CT)	1	$ 0.38
		10	$ 0.28
		25	$ 0.25
		100	$ 0.16
		250	$ 0.13
		500	$ 0.11
		1000	$ 0.08
	Digi-Reel®	1	$ 0.38
		10	$ 0.28
		25	$ 0.25
		100	$ 0.16
		250	$ 0.13
		500	$ 0.11
		1000	$ 0.08
	Tape & Reel (TR)	3000	$ 0.07
		6000	$ 0.06
		15000	$ 0.06
		30000	$ 0.05
		75000	$ 0.05
		150000	$ 0.05
Texas Instruments	LARGE T&R	1	$ 0.10
		100	$ 0.07
		250	$ 0.05
		1000	$ 0.04

Description

General part information

SN74LVC1G175 Series

This single D-type flip-flop is designed for 1.65-V to 5.5-V VCCoperation.

The SN74LVC1G175 device has an asynchronous clear (CLR) input. WhenCLRis high, data from the input pin (D) is transferred to the output pin (Q) on the clock's (CLK) rising edge. WhenCLRis low, Q is forced into the low state, regardless of the clock edge or data on D.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

Documents

Technical documentation and resources

SN74LVC1G175DBVR

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SN74LVC1G175DBVR

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Technical Specifications

SN74LVC1G175 Series

Pricing

Description

SN74LVC1G175 Series

Documents

CMOS Power Consumption and CPD Calculation (Rev. B)

Input and Output Characteristics of Digital Integrated Circuits

LVC Characterization Information

Selecting the Right Level Translation Solution (Rev. A)

Push-Button Circuit (Rev. B)

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Use of the CMOS Unbuffered Inverter in Oscillator Circuits

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

LOGIC Pocket Data Book (Rev. B)

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

How to Select Little Logic (Rev. A)

TI IBIS File Creation, Validation, and Distribution Processes

Texas Instruments Little Logic Application Report

Signal Switch Data Book (Rev. A)

SN74LVC1G175 Single D-Type Flip-Flop With Asynchronous Clear datasheet (Rev. G)

Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices

Logic Guide (Rev. AB)

Understanding Advanced Bus-Interface Products Design Guide

Design Summary for WCSP Little Logic (Rev. B)

Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices

Generate an Enable Signal that can be Toggled

16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)

Power-Up Behavior of Clocked Devices (Rev. B)

Live Insertion

STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS

Implications of Slow or Floating CMOS Inputs (Rev. E)

Standard Linear & Logic for PCs, Servers & Motherboards

Low-Voltage Logic (LVC) Designer's Guide

Little Logic Guide 2018 (Rev. G)

LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)

SN74LVC1G175 Series