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Technical Specifications
Parameters and characteristics for this part
| Specification | AD561JCHIPS |
|---|---|
| Architecture | R-2R |
| Data Interface | Parallel |
| Differential Output | False |
| INL/DNL (LSB) | 0.5 LSB, 0.25 LSB |
| Mounting Type | Surface Mount |
| Number of Bits [custom] | 10 |
| Operating Temperature [Max] | 70 °C |
| Operating Temperature [Min] | 0 °C |
| Output Type | Current - Unbuffered |
| Package / Case | Die |
| Reference Type | Internal |
| Settling Time | 250 ns |
| Supplier Device Package | Die |
| Voltage - Supply, Analog [Max] | 16.5 V |
| Voltage - Supply, Analog [Min] | 4.5 V, -10.8 V |
| Voltage - Supply, Digital [Max] | 16.5 V |
| Voltage - Supply, Digital [Min] | 4.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
Description
General part information
JM38510/13301 Series
The AD561 is an integrated circuit 10-bit digital-to-analog converter combined with a high stability voltage reference fabricated on a single monolithic chip. Using ten precision high-speed current-steering switches, a control amplifier, voltage reference, and laser-trimmed thin-film SiCr resistor network, the device produces a fast, accurate analog output current. Laser trimmed output application resistors are also included to facilitate accurate, stable current-to-voltage conversion; they are trimmed to 0.1% accuracy, thus eliminating external trimmers in many situations.Several important technologies combine to make the AD561 the most accurate and most stable 10-bit DAC available. The low temperature coefficient, high stability thin-film network is trimmed at the wafer level by a fine resolution laser system to 0.01% typical linearity. This results in an accuracy specification of ±1/4 LSB max for the K and T versions, and 1/2 LSB max for the J and S versions.The AD561 also incorporates a low noise, high stability subsurface zener diode to produce a reference voltage with excellent long term stability and temperature cycle characteristics, which challenge the best discrete Zener references. A temperature compensation circuit is laser-trimmed to allow custom correction of the temperature coefficient of each device. This results in a typical full-scale temperature coefficient of 15 ppm/°C; the TC is tested and guaranteed to 30 ppm/°C max for the K and T versions, 60 ppm/°C max for the S, and 80 ppm/°C for the J.The AD561 is available in four performance grades. The AD561J and K are specified for use over the 0°C to +70°C temperature range and are available in either a 16-pin hermetically-sealed ceramic DIP or a 16-pin molded plastic DIP. The AD561S and T grades are specified for the -55°C to +125°C range and are available in the ceramic package.
Documents
Technical documentation and resources
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