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SN74CB3Q16211DGGR
Integrated Circuits (ICs)

SN74ABT16833DGGR

Obsolete
Texas Instruments

IC TXRX NON-INVERT 5.5V 56TSSOP

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SN74CB3Q16211DGGR
Integrated Circuits (ICs)

SN74ABT16833DGGR

Obsolete
Texas Instruments

IC TXRX NON-INVERT 5.5V 56TSSOP

Deep-Dive with AI

DocumentsDatasheet

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74ABT16833DGGR
Current - Output High, Low [custom]64 mA
Current - Output High, Low [custom]32 mA
Mounting TypeSurface Mount
Number of Bits per Element [custom]8
Number of Elements2
Operating Temperature [Max]85 C
Operating Temperature [Min]-40 ¯C
Output TypePush-Pull
Package / Case56-TFSOP
Package / Case [x]0.24 in
Package / Case [y]6.1 mm
Supplier Device Package56-TSSOP
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]4.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyN/A 0$ 1.45
9900$ 1.45

Description

General part information

74ABT16833 Series

The 'ABT16833 consist of two noninverting 8-bit to 9-bit parity bus transceivers and are designed for communication between data buses. For each transceiver, when data is transmitted from the A bus to the B bus, an odd-parity bit is generated and output on the parity I/O pin (1PARITY or 2PARITY). When data is transmitted from the B bus to the A bus, 1PARITY (or 2PARITY) is configured as an input and combined with the B-input data to generate an active-low error flag if odd parity is not detected.

The error (1or 2) output is configured as an open-collector output. The B-to-A parity-error flag is clocked into 1(or 2) on the low-to-high transition of the clock (1CLK or 2CLK) input. 1(or 2) is cleared (set high) by taking the clear (1or 2) input low.

The output-enable (and) inputs can be used to disable the device so that the buses are effectively isolated. When bothandare low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic capability.

Documents

Technical documentation and resources