SN74ABT16833DLR
ActiveDUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
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SN74ABT16833DLR
ActiveDUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74ABT16833DLR |
|---|---|
| Current - Output High, Low [custom] | 64 mA |
| Current - Output High, Low [custom] | 32 mA |
| Mounting Type | Surface Mount |
| Number of Bits per Element [custom] | 8 |
| Number of Elements | 2 |
| Operating Temperature [Max] | 85 C |
| Operating Temperature [Min] | -40 ¯C |
| Output Type | Push-Pull |
| Package / Case | 56-BSSOP |
| Package / Case [x] | 0.295 in |
| Package / Case [y] | 7.5 mm |
| Supplier Device Package | 56-SSOP |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 4.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 3.05 | |
| Digi-Reel® | 1 | $ 3.05 | ||
| N/A | 0 | $ 1.62 | ||
| 24000 | $ 1.62 | |||
| Tape & Reel (TR) | 1000 | $ 1.61 | ||
| 2000 | $ 1.53 | |||
| 5000 | $ 1.48 | |||
| Texas Instruments | LARGE T&R | 1 | $ 2.31 | |
| 100 | $ 2.02 | |||
| 250 | $ 1.42 | |||
| 1000 | $ 1.14 | |||
Description
General part information
74ABT16833 Series
The 'ABT16833 consist of two noninverting 8-bit to 9-bit parity bus transceivers and are designed for communication between data buses. For each transceiver, when data is transmitted from the A bus to the B bus, an odd-parity bit is generated and output on the parity I/O pin (1PARITY or 2PARITY). When data is transmitted from the B bus to the A bus, 1PARITY (or 2PARITY) is configured as an input and combined with the B-input data to generate an active-low error flag if odd parity is not detected.
The error (1or 2) output is configured as an open-collector output. The B-to-A parity-error flag is clocked into 1(or 2) on the low-to-high transition of the clock (1CLK or 2CLK) input. 1(or 2) is cleared (set high) by taking the clear (1or 2) input low.
The output-enable (and) inputs can be used to disable the device so that the buses are effectively isolated. When bothandare low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic capability.
Documents
Technical documentation and resources