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TVSOP (DGV)
Integrated Circuits (ICs)

SN74LV373ADGVR

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Texas Instruments

OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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TVSOP (DGV)
Integrated Circuits (ICs)

SN74LV373ADGVR

Active
Texas Instruments

OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74LV373ADGVR
Circuit [custom]8
Circuit [custom]8
Current - Output High, Low [custom]16 mA
Current - Output High, Low [custom]16 mA
Delay Time - Propagation1 ns
Independent Circuits1
Logic TypeD-Type Transparent Latch
Mounting TypeSurface Mount
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Output TypeTri-State
Package / Case20-TFSOP
Package / Case [y]4.4 mm
Package / Case [y]0.173 in
Supplier Device Package20-TVSOP
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]2 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 0.84
10$ 0.74
25$ 0.69
100$ 0.56
250$ 0.52
500$ 0.45
1000$ 0.36
Digi-Reel® 1$ 0.84
10$ 0.74
25$ 0.69
100$ 0.56
250$ 0.52
500$ 0.45
1000$ 0.36
Tape & Reel (TR) 2000$ 0.32
6000$ 0.30
10000$ 0.29
Texas InstrumentsLARGE T&R 1$ 0.63
100$ 0.48
250$ 0.35
1000$ 0.25

Description

General part information

SN74LV373A-Q1 Series

The SN74LV373AT is an octal transparent D-type latch. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

OEdoes not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.